Abstract: A method for testing a system on a chip or a system on a package (““SOPC”) having a plurality of internal modules that are tested to determine whether predetermined performance specifications are satisfied. A first module of the SOPC is selected for testing. A determination is made as to whether the first module is directly accessible or not. If the first module is directly accessible, the module may be tested with automated test equipment external to the SOPC. If the first module is not directly accessible, the module may be tested with a second and third module of the SOPC.
Type:
Grant
Filed:
October 24, 2002
Date of Patent:
November 8, 2005
Assignee:
Ardext Technologies, Inc.
Inventors:
Abhijit Chatterjee, Dave Majernik, Sasikumar Cherubal, Sudip Chakrabarti, Ramakrishna Voorakaranam, Jacob A. Abraham, Douglas Goodman