Patents Assigned to ARE Corp.
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Patent number: 9668705Abstract: An X-ray tomographic imaging apparatus includes an X-ray and a direct conversion type of detector. The X-ray tube and the detector are supported by the support means so as to be rotatable along curved orbits mutually independently. Under instructions from a computer, scans and image reconstruction are performed. The X-ray tube and the detector are moved along the orbits mutually independently so that X-ray beams are always transmitted through a desired tomographic plane of an object at desired angles. Acquired frame data are used to produce a panoramic image of the plane, while the frame data and the panoramic image are used to produce a tomographic image in which structural components of the object are optically focused and distortions caused due to differences in X-ray paths are suppressed. The apparatus can be used as devices for dental, medical diagnosis and nondestructive inspection, and can have a CT imaging function.Type: GrantFiled: July 13, 2011Date of Patent: June 6, 2017Assignee: TAKARA TELESYSTEMS CORP.Inventors: Tsutomu Yamakawa, Masahiro Tsujita, Akitoshi Katsumata, Koichi Ogawa, Hisatoshi Aoki
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Patent number: 9670481Abstract: Disclosed are methods for identifying desired members from a display libraries, including bacteriophage display libraries. Display library members can be amplified in the presence of a target compound so that cycles of selection can be rapidly completed.Type: GrantFiled: October 8, 2013Date of Patent: June 6, 2017Assignee: Dyax Corp.Inventors: Robert Charles Ladner, Shannon Hogan, Kristin L. Rookey
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Patent number: 9670092Abstract: Certain example embodiments of this invention relate to articles including anticondensation and/or low-E coatings that are exposed to an external environment, and/or methods of making the same. In certain example embodiments, the anticondensation and/or low-E coatings may be survivable in an outside environment. The coatings also may have a sufficiently low sheet resistance and hemispherical emissivity such that the glass surface is more likely to retain heat from the interior area, thereby reducing (and sometimes completely eliminating) the presence condensation thereon. The articles of certain example embodiments may be, for example, skylights, vehicle windows or windshields, IG units, VIG units, refrigerator/freezer doors, and/or the like.Type: GrantFiled: December 23, 2015Date of Patent: June 6, 2017Assignee: Guardian Industries Corp.Inventors: Jean-Marc Lemmer, Nestor P. Murphy, David D. McLean, Richard Blacker
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Patent number: 9673698Abstract: The invention provides a voltage regulator with multiple output ranges. The voltage regulator includes a voltage divider that has at least a first resistor and a second resistor. The resistance ratio of the first resistor to the second resistor is 1:(X?1). The input of the regulator is connected to the first resistor, and the output is connected to the second resistor. A voltage source may provide a reference voltage Vref to a connecting point between the first resistor and the second resistor. At least one working circuit is connected to the output to provide the output voltage as Vout=Vin?X(Vin?Vref), wherein Vin is the input voltage. As another option, the at least one working circuit may be deactivated and the output may be coupled to ground.Type: GrantFiled: November 9, 2014Date of Patent: June 6, 2017Assignee: CISTA SYSTEM CORP.Inventors: Li Guo, Guangbin Zhang
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Patent number: 9673808Abstract: A power-on-reset circuit including a first diode-connected transistor, a second diode-connected transistor, a resistor and a current comparator circuit is provided. A cathode of the first diode-connected transistor is coupled to a reference voltage. A first end of the resistor is coupled to a power voltage. A second end of the resistor is coupled to an anode of the first diode-connected transistor. A cathode of the second diode-connected transistor is coupled to the reference voltage. An anode of the second diode-connected transistor is coupled to the first end of the resistor. The current comparator circuit is coupled to the first diode-connected transistor and the second diode-connected transistor. The current comparator circuit compares a current of the first diode-connected transistor with a current of the second diode-connected transistor to obtain a comparing result, wherein the comparing result determines a reset signal.Type: GrantFiled: March 10, 2016Date of Patent: June 6, 2017Assignee: Faraday Technology Corp.Inventors: Kai-Neng Tang, Chi-Sheng Liao
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Patent number: 9671328Abstract: A system for classifying different types of sheeting materials of road signs depicted in a videostream compares estimated retroreflectivity values against known minimum retroreflectivity values for each of a plurality of colors. Once a road sign has been identified in the videostream, the frames associated with that road sign are analyzed to determine each of a plurality of colors present on the road sign. An estimated retroreflectivity for each of the plurality of colors present on the road sign is then determined. By comparing the estimated retroreflectivity for each of the plurality of colors against known minimum retroreflectivity values for the corresponding color for different types of sheeting materials, an accurate determination of the classification of the sheeting material of the road sign is established. Preferably, certain conditions of gross failure of the sheeting material are filtered out before classification of the sheeting material is determined.Type: GrantFiled: May 6, 2016Date of Patent: June 6, 2017Assignee: Facet Technology Corp.Inventors: James E. Retterath, Robert A. Laumeyer
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Patent number: 9673324Abstract: The present invention provides a metal oxide semiconductor (MOS) device, including a substrate, a gate structure on the substrate and a source/drain region disposed in the substrate at one side of the gate structure and in at least a part of an epitaxial structure, wherein the epitaxial structure includes a first buffer layer, which is an un-doped buffer layer, including a bottom portion disposed on a bottom surface of the epitaxial structure and a sidewall portion disposed on a concave sidewall of the epitaxial structure, an epitaxial layer which is encompassed by the first buffer layer, and a semiconductor layer which is disposed between the first buffer layer and the epitaxial layer. The source/drain region is disposed in the epitaxial structure.Type: GrantFiled: August 24, 2016Date of Patent: June 6, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tien-I Wu, I-Cheng Hu, Yu-Shu Lin, Shu-Yen Chan, Neng-Hui Yang
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Patent number: 9671798Abstract: Embodiments of the present invention are directed to a customizable bio-manufacturing system which includes a manufacturing space having a first air handling system for providing supply air and a second air handling system for handling exhaust air, the supply air system being optionally provided with at least one of filtration, heating, cooling and or humidity control and a plurality of portable modules provided within the manufacturing space. At least one module having an interior capable of being interconnected with another module interior and each module's interior includes one or more components to perform at least one specific task of a biological, chemical, and/or pharmaceutical manufacturing process. At least one module includes an on-board environmental control system for controlling an environment within the module and a connection means for interconnecting the module interior with another module interior.Type: GrantFiled: October 11, 2012Date of Patent: June 6, 2017Assignee: GE HEALTHCARE BIO-SCIENCES CORP.Inventors: Geoffrey L. Hodge, Parrish M. Galliher, Michael Fisher
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Patent number: 9673318Abstract: A semiconductor device includes a semiconductor substrate having a base region situated over a drift region, a source trench extending through the base region and into the drift region, the source trench having a shield electrode, a gate trench extending through the base region and into the drift region, the gate trench adjacent the source trench, the gate trench having a gate electrode situated above a buried electrode. The source trench is surrounded by the gate trench. The shield electrode is coupled to a source contact over the semiconductor substrate. The semiconductor device also includes a source region over the base region. The gate trench includes gate trench dielectrics lining a bottom and sidewalls of the gate trench. The source trench includes source trench dielectrics lining a bottom and sidewalls of the source trench.Type: GrantFiled: January 13, 2016Date of Patent: June 6, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Ashita Mirchandani, Timothy D. Henson
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Patent number: 9672514Abstract: Systems and methods are provided for performing transactions and managing communications using a trusted third party. In one embodiment, a sender transfers an encrypted version of a file (such as a digitally encoded audio track, movie, document, or the like) to someone who wishes to receive it. The receiver computes a first hash of at least a portion of the encrypted data content, and sends the first hash to a third party configured to compare at least a portion of the first hash to at least a portion of a second hash. The receiver receives a file decryption key from the third party, and decrypts at least the portion of the received encrypted data content with the decryption key. In some cases, multiple hashes of the encrypted data content may be computed, each using a different portion of the encrypted data content.Type: GrantFiled: August 28, 2015Date of Patent: June 6, 2017Assignee: Intertrust Technologies Corp.Inventors: Binyamin Pinkas, Tomas Sander, William G. Horne
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Controlling a switched capacitor bank in a voltage controlled oscillator for wireless sensor devices
Patent number: 9673755Abstract: In some aspects, a wireless sensor device includes a voltage controlled oscillator. The voltage controlled oscillator includes a resonator circuit, a multiplexer and control logic. The resonator circuit includes a switched capacitor bank operable to tune the resonator circuit. The multiplexer is communicatively coupled to the switched capacitor bank to select combinations of capacitor bank elements based on input values representing digital capacitance levels. The multiplexer includes a first multi-bit input configured to receive a first set of values representing a first combination of the capacitor bank elements; a second multi-bit input configured to receive a second set of values representing a second combination of the capacitor bank elements; and a multi-bit output configured to communicate the first or second set of values to the switched capacitor bank. The control logic is configured to generate the first and second sets of values for each of the digital capacitance levels.Type: GrantFiled: February 9, 2016Date of Patent: June 6, 2017Assignee: Cognitive Systems Corp.Inventors: Volodymyr Yavorskyy, Tajinder Manku -
Patent number: 9673800Abstract: An analog switch circuit is disclosed. The analog switch circuit includes a MOSFET and a control switch. The MOSFET includes a drain electrode, a source electrode, a gate electrode, and a body electrode. A gate bias is applied on the gate electrode to control whether the MOSFET is ON or OFF. The control switch includes a control terminal, a first terminal, a second terminal, and a third terminal. A control bias relating to the gate bias is applied to the control terminal so that the first terminal is connected to the second terminal when the MOSFET is ON, and the first terminal is connected to the third terminal when the MOSFET is OFF. The second terminal is connected to a first voltage source providing a first bias. The third terminal is connected to a second voltage source providing a second bias different from the first bias.Type: GrantFiled: February 19, 2016Date of Patent: June 6, 2017Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Guan-Yu Chen, Leaf Chen
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Patent number: 9673186Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: GrantFiled: March 31, 2015Date of Patent: June 6, 2017Assignee: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro Takatani, Hsien-Fu Hsiao, Cheng-Kuo Lin, Chang-Hwang Hua
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Patent number: 9672758Abstract: A kit for replicating an implantable prosthetic devices includes a model implant, a geometric tool, and an insert. The model implant may include a first curved surface, and the first curved surface may include a first cutout formed. The geometric tool may include a second curved surface having a second cutout. The geometric configuration of the second cutout may be substantially identical to the geometric configuration of the first cutout of the model implant. The insert may be configured to be engaged with both the first cutout and the second cutout.Type: GrantFiled: April 26, 2012Date of Patent: June 6, 2017Assignee: Howmedica Osteonics Corp.Inventor: Sujit Sivadas
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Patent number: 9673776Abstract: A wide band directional coupler comprises a first transmission line, a second transmission line and at least one inductor, wherein the first transmission line and the second transmission line are adjacent each other, and the inductor connects to the second transmission. As a RF signal passes through the first transmission line, the second transmission line will couple with the RF signal in the first transmission line to generate a coupling signal. The inductor is connected to the second transmission line to improve the coupling factor and/or the insertion loss of the wide band directional coupler at high frequency band.Type: GrantFiled: July 21, 2015Date of Patent: June 6, 2017Assignee: Airoha Technology Corp.Inventor: Kuan-Wei Li
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Patent number: 9674418Abstract: Disclosed are a two-way photographing system of a mobile terminal and a control method. The system includes a rotating mirror, a lens and an approach sensing apparatus. The rotating mirror is rotatable around the axis to a front reflection state or a rear reflection state for reflecting the incident light to the lens. The rotating minor has a first end close to the front light entrance and a second end close to the rear light entrance. The approach sensing apparatus is located adjacent to the first end when the rotating minor is in the front reflection state or adjacent to the second end when the rotating mirror is in the rear reflection state, and configured to generate a first detecting signal when the rotating mirror is in the front reflection state and to generate a second detecting signal when the rotating mirror is in the rear reflection state.Type: GrantFiled: February 24, 2014Date of Patent: June 6, 2017Assignee: GUANG DONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.Inventors: Yuanqing Zeng, Chengyu Wu
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Patent number: 9673049Abstract: A manufacturing method of a patterned structure of a semiconductor device includes following steps. A plurality of support features are formed on a substrate. A first conformal spacer layer is formed on the support features and a surface of the substrate, a second conformal spacer layer is formed on the first conformal spacer layer, and a covering layer is formed on the second conformal spacer layer. A gap between the support features is filled with the first conformal spacer layer, the second conformal spacer layer, and the covering layer. A first process is performed to remove a part of the covering layer, the second conformal spacer layer, and the first conformal spacer layer. A second process is performed to remove the support features or the first conformal spacer layer between the support feature and the second conformal spacer layer to expose a part of the surface of the substrate.Type: GrantFiled: April 9, 2015Date of Patent: June 6, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Yu-Cheng Tung
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Patent number: 9669219Abstract: Therapy systems for treating a patient are disclosed. Representative therapy systems include an implantable pulse generator, a signal delivery device electrically coupled to the pulse generator, and a remote control in electrical communication with the implantable pulse generator. The pulse generator can have a computer-readable medium containing instructions for performing a process that comprises collecting the patient status and stimulation parameter; analyzing the collected patient status and stimulation parameter; and establishing a preference baseline containing a preferred stimulation parameter corresponding to a particular patient status.Type: GrantFiled: November 17, 2015Date of Patent: June 6, 2017Assignee: Nevro Corp.Inventors: Anthony V. Caparso, Jon Parker, Andre B. Walker, Yougandh Chitre
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Patent number: 9673100Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.Type: GrantFiled: November 10, 2014Date of Patent: June 6, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen, Chien-Ting Lin, Shih-Fang Tzou, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen
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Patent number: D788861Type: GrantFiled: October 19, 2015Date of Patent: June 6, 2017Assignee: Total Gym Global Corp.Inventors: Thomas J. Campanaro, Jesse Thomas Campanaro, Dan McCutcheon