Patents Assigned to ARE Corp.
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Publication number: 20220406996Abstract: A manufacturing method of a memory device includes the following steps. Memory units are formed on a substrate. Each of the memory units includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a sidewall portion of the non-conformal spacer layer and a sidewall portion of the conformal spacer layer in the vertical direction.Type: ApplicationFiled: July 15, 2021Publication date: December 22, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Kuo, Chung-Yi Chiu
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Publication number: 20220402460Abstract: A wiper controlling method and apparatus are provided. The wiper controlling apparatus obtains an area of a Pulse Width Modulation (PWM) control signal generated for driving a wiper motor while a wiper moves in a pre-defined section and controls a speed of the wiper based on a result of comparing the area with at least one pre-defined reference value.Type: ApplicationFiled: May 25, 2022Publication date: December 22, 2022Applicant: DY-ESSYS CORP.Inventors: Min Wook PARK, Je Min MUN, Ki Chan LEE
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Publication number: 20220405032Abstract: An information processing apparatus includes a processor configured to receive a printing request for a document that is based on a spoken voice of a user and includes a designation of a specific element among plural elements constituting the document, and perform a control for printing a part including the specific element of the document.Type: ApplicationFiled: November 8, 2021Publication date: December 22, 2022Applicant: FUJIFILM Business Innovation Corp.Inventors: Koichi SATO, Kiyoshi YASUKAWA
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Publication number: 20220406902Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.Type: ApplicationFiled: August 24, 2022Publication date: December 22, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Chieh Wang, Po-Chun Lai, Ke-Feng Lin, Chen-An Kuo, Ze-Wei Jhou
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Publication number: 20220402888Abstract: Novel co-crystal and eutectic crystal of kojic acid and a co-former that are excellent in physical properties are provided. In one aspect, novel co-crystals of kojic acid and a co-former that is maltol or ethyl maltol are provided. In another aspect, novel crystal of a eutectic mixture of kojic acid and a co-former that is selected from the group consisting of, maltol, ethyl maltol, methyl paraben and propyl gallate are provided. Methods for producing the novel co-crystal or eutectic crystal are also described. The novel co-crystals and eutectic crystals may be included in a pharmaceutical composition, a health food product or a medical food product for the treatment and/or prophylaxis of a neuropsychiatric disorder.Type: ApplicationFiled: July 15, 2022Publication date: December 22, 2022Applicant: SyneuRx International (Taiwan) Corp.Inventors: Guo-Chuan Emil TSAI, Ching-Cheng WANG, Tien-Lan HSIEH
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Publication number: 20220404849Abstract: A voltage-to-current converter includes a first transistor having a drain coupled to a first node, a second transistor having a drain coupled to the first node, an operational amplifier having a first input terminal configured to receive a reference voltage and a second input terminal coupled to a source of the first transistor or a source of the second transistor, a control circuit having an input terminal coupled to an output terminal of the operational amplifier, a first output terminal coupled to a gate of the first transistor, and a second output terminal coupled to a gate of the second transistor, a first resistor coupled between the source of the first transistor and a ground, and a second resistor coupled between the source of the second transistor and the ground. An output current of the voltage-to-current converter is generated from the first node.Type: ApplicationFiled: June 17, 2021Publication date: December 22, 2022Applicant: NOVATEK Microelectronics Corp.Inventor: Hsiang-Yi Chiu
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Publication number: 20220401164Abstract: Surgical systems, methods and surgical planning programs to facilitate preparation of an anatomical cavity to receive a cup implant. The system includes a control system, a localizer and a robotic manipulator configured to move an energy applicator that is adapted to remove tissue. The control system obtains or generates a surgical plan that defines characteristics of cement holes to be formed within a wall of the anatomical cavity for receiving bone cement. The control system registers the surgical plan to the anatomical cavity with the localizer and controls the robotic manipulator to utilize the energy applicator to form the cement holes within the wall of the anatomical cavity according to the surgical plan.Type: ApplicationFiled: August 24, 2022Publication date: December 22, 2022Applicant: MAKO Surgical Corp.Inventors: John Timperley, Ross Crawford, Jonathan Howell, Matthew Hubble, Matthew Wilson, Matthew Thompson, Graham Gie
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Publication number: 20220406349Abstract: The disclosure provides a semiconductor storage device that realizes high integration and improves reliability. A bit line selection circuit (100) of a flash memory includes transistors (BLSeO, BLSeE, BLSoO, BLSoE) in the column direction of bit lines (BL0-BL3), selecting a bit line pair composed of an even-numbered bit line (BL0) and an odd-numbered bit line (BL3) is selected by the transistors, in which a bit line pair (BL1, BL2) adjacent to the selected bit line pair is set as a non-selected bit line pair, and the selected bit line pair (BL0, BL3) is connected to page buffer/sensing circuit through an output node (BLS0, BLS1).Type: ApplicationFiled: June 16, 2022Publication date: December 22, 2022Applicant: Winbond Electronics Corp.Inventor: Naohito Morozumi
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Publication number: 20220408547Abstract: A method for manufacturing an embedded component structure includes providing a circuit board having a through hole and a heat dissipation layer; disposing a chip in the through hole; forming a dielectric layer on a first surface and a second surface of the circuit board to seal the chip and cover a lower surface of the heat dissipation layer; removing a first part of the dielectric layer to form a first opening from which a upper surface of the heat dissipation layer is exposed and a second opening from which the lower surface of the heat dissipation layer is exposed; and forming a thermal conductive material layer in the first and the second opening to form a heat dissipation element surrounding the chip. The upper surface of the heat dissipation layer is exposed from the through hole. The chip, the circuit board, and the heat dissipation element are electrically connected.Type: ApplicationFiled: August 25, 2022Publication date: December 22, 2022Applicant: Unimicron Technology Corp.Inventor: Yu-Shen Chen
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Publication number: 20220406846Abstract: A method of forming the semiconductor device is provided. The method includes following steps. A memory structure is formed over a first conductive line over a substrate and is electrically connected to the first conductive line. A sacrificial layer is formed on the memory structure. A spacer layer is formed to cover the memory structure and the sacrificial layer. A first dielectric layer is formed to cover the spacer layer. A planarization process is performed to remove a portion of the first dielectric layer. A second dielectric layer is formed on the spacer layer and the first dielectric layer. A patterning process is performed to form an opening exposing a portion of the top surface of the sacrificial layer. The sacrificial layer is removed to form a recess. A second conductive line is formed in the opening and the recess to be electrically coupled to the memory structure.Type: ApplicationFiled: August 29, 2022Publication date: December 22, 2022Applicant: Winbond Electronics Corp.Inventors: Yung-Han Chiu, Shu-Ming Li, Po-Yen Hsu
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Publication number: 20220403272Abstract: There are provided systems and methods for using fuel-rich partial oxidation to produce an end product from waste gases, such as flare gas. In an embodiment, the system and method use air-breathing piston engines and turbine engines for the fuel-rich partial oxidation of the flare gas to form synthesis gas, and reactors to convert the synthesis gas into the end product. In an embodiment the end product is methanol.Type: ApplicationFiled: May 17, 2022Publication date: December 22, 2022Applicant: Obantarla Corp.Inventors: John Anthony Dean, Bunmi Tolu Adekore, Paul E. Yelvington, Joshua B. Browne, Andrew Randolph
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Publication number: 20220406904Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.Type: ApplicationFiled: August 25, 2022Publication date: December 22, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Chieh Wang, Po-Chun Lai, Ke-Feng Lin, Chen-An Kuo, Ze-Wei Jhou
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Publication number: 20220405464Abstract: An information processing apparatus includes a processor configured to receive an area in a document from a first user and set in the received area an exclusive area that is not editable by a user other than the first user.Type: ApplicationFiled: November 21, 2021Publication date: December 22, 2022Applicant: FUJIFILM Business Innovation Corp.Inventor: Takenori MATSUO
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Publication number: 20220406800Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).Type: ApplicationFiled: July 21, 2021Publication date: December 22, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsueh-Chun Hsiao, Yi-Ning Peng, Tzu-Yun Chang
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Publication number: 20220405710Abstract: An information processing apparatus includes a processor configured to provide plural users with a shared workspace for the plural users to share and work on a file, in a case where a condition of allowing use of the shared workspace is satisfied, perform control to display a first button for receiving an instruction to transfer the file to a personal workspace in which the user personally performs work, and in a case where the first button is singly operated by the user, cause the file to be transferred from the shared workspace to the personal workspace.Type: ApplicationFiled: November 25, 2021Publication date: December 22, 2022Applicant: FUJIFILM Business Innovation Corp.Inventor: Kazuya IIMURA
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Publication number: 20220406903Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.Type: ApplicationFiled: August 24, 2022Publication date: December 22, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Chieh Wang, Po-Chun Lai, Ke-Feng Lin, Chen-An Kuo, Ze-Wei Jhou
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Publication number: 20220402044Abstract: A cutting tool includes: a substrate; and a coating film disposed on the substrate, wherein the coating film includes an ?-Al2O3 layer, the ?-Al2O3 layer includes a plurality of ?-Al2O3 crystal grains, and has a TC(006) of more than 5 in texture coefficient TC(hkl), and an elastic modulus E1 of the ?-Al2O3 layer at a room temperature and an elastic modulus E2 of the ?-Al2O3 layer at 800° C. represent a relation of the following expression B-1: 0<{(E1?E2)/E1}×100<10??Expression B-1.Type: ApplicationFiled: June 11, 2020Publication date: December 22, 2022Applicant: Sumitomo Electric Hardmetal Corp.Inventors: Yasuki KIDO, Susumu OKUNO, Masahito HIKIJI
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Publication number: 20220401906Abstract: There are provided systems and methods for using fuel-rich partial oxidation to produce an end product from waste gases, such as flare gas. In an embodiment, the system and method use air-breathing piston engines and turbine engines for the fuel-rich partial oxidation of the flare gas to form synthesis gas, and reactors to convert the synthesis gas into the end product. In an embodiment the end product is methanol.Type: ApplicationFiled: May 17, 2022Publication date: December 22, 2022Applicant: Obantarla Corp.Inventors: John Anthony Dean, Bunmi Tolu Adekore, Paul E. Yelvington, Joshua B. Browne, Andrew Randolph
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Publication number: 20220408344Abstract: The application discloses a relay method, a routing table generation method and apparatus, a terminal and a storage medium. The relay method is applied to a relay UE. The relay UE comprises a relay protocol stack, the relay protocol stack being located between a PDCP layer and a layer 2 protocol stack of a PC5 interface, or the relay protocol stack being a MAC layer protocol stack, and the relay protocol stack comprising a relay receiving entity and a relay sending entity. The relay method comprises: the relay receiving entity receiving a relay protocol data unit (PDU) sent by a last hop node, and forwarding the relay PDU to the relay sending entity; and the relay sending entity sending the relay PDU to a next hop node according to a protocol header of the relay PDU, the relay PDU being a PDU sent between at least two remote UEs.Type: ApplicationFiled: August 18, 2022Publication date: December 22, 2022Applicant: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.Inventor: Qianxi LU
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Publication number: 20220407129Abstract: Embodiments of a device and methods to operating the same are described that can provide high level status information about a battery having multiple modular battery packs which may be arranged in different numbers and/or electrical configurations depending on the specific application. In some embodiments, a smart hub is in communication with battery packs within the battery and configured to selectively query low level status information associated with individual battery packs based on a stored pack configuration that can be updated by a user. The device allows more efficient provision of battery information during flexible assembly and connection of the battery packs.Type: ApplicationFiled: December 18, 2020Publication date: December 22, 2022Applicant: Dragonfly Energy Corp.Inventor: Denis Phares
