Abstract: A Content-Addressable Memory (CAM) cell has a latch of cross-coupled inverters and transmission gates to bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing. A node in the latch is applied to a gate of a data transistor in series with a select transistor to discharge a match line when select and latch data mismatch. Second data and select transistors receive inverse data from the latch for a CAM but receive data from a second cell latch for a Ternary Content-Addressable Memory (TCAM) cell with two latches per pair of select lines. When mismatches occur, even cells discharge the match line using n-channel data and select transistors while odd cells charge a complement match line using p-channel data and select transistors. The total number of p-channel and n-channel transistors in the cell can be equal when using complementary match lines.

Abstract: A Content-Addressable Memory (CAM) cell has a latch of cross-coupled inverters and transmission gates to bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing. A node in the latch is applied to a gate of a data transistor in series with a select transistor to discharge a match line when select and latch data mismatch. Second data and select transistors receive inverse data from the latch for a CAM but receive data from a second cell latch for a Ternary Content-Addressable Memory (TCAM) cell with two latches per pair of select lines. When mismatches occur, even cells discharge the match line using n-channel data and select transistors while odd cells charge a complement match line using p-channel data and select transistors. The total number of p-channel and n-channel transistors in the cell can be equal when using complementary match lines.

Abstract: A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

Abstract: A Field-Programmable Gate Array (FPGA) RAM cell has cross-coupled inverters and transmission gates to bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing and reading in configuration mode, but remain off for mission mode when the FPGA performs the configured logic functions. For configurable switching fabric, the FPGA RAM cell has nodes from the cross-coupled inverters drive gates of p-channel and n-channel transistors in parallel that form a transmission gate between a switch input and a switch output in the configurable switching fabric. For configurable logic blocks, the FPGA RAM cell has a node from the cross-coupled inverters driving gates of p-channel and n-channel data transistors in a four-transistor stack with p-channel and n-channel select transistors controlled by a logic input. The row of FPGA RAM cells store a Look-Up Table (LUT) and perform first-level muxing.

Abstract: An eight-transistor (8T) Static Random-Access Memory (SRAM) cell has four latch transistors, and pairs of n-channel and p-channel pass transistors in parallel to only one pair of bit lines. During read, only the read word line and the n-channel pass transistors are activated, but during a write both the read word line and an extra write word line are activated to turn on all four pass transistors. The cell is powered by VDDM, one threshold above the normal VDD power supply of the read sense and write drivers and interfaces. The bit lines are precharged to VDD but pulled up to VDDM by a latch of cross-coupled p-channel transistors. Any p-channel transistors that connect to the bit lines are driven inactive by VDDM. The read margin is largely decoupled from the write margin by two additional p-channel pass transistors and one extra word line versus a standard 6T cell.