Abstract: A data processing device which includes a common memory connecting mechanism which is located between a memory bus to which copyback cache is connected, and a common memory. The common memory connecting mechanism includes a slave type transfer mechanism which directly assesses the common memory bypassing the cache and processes thereof, and a data mover which transfers data between the common memory and main memory.
Type:
Grant
Filed:
January 10, 1991
Date of Patent:
January 4, 1994
Assignees:
Hitachi, Ltd., Arix Computer
Inventors:
Hiroaki Fukumaru, Siochi Takaya, Yoshihiro Miyazaki, Daniel M. McCarthy