Abstract: A data processing apparatus is operable in a either a self-test mode or an operational mode. The apparatus comprises a plurality of functional units, at least one of the functional units being operable to perform data processing operations and at least a subset of the plurality of functional units having at least one of a respective co-processor register for storing configuration data, a respective debug register for storing debug data and a respective functional unit memory. A memory self-test controller operable in the self-test mode to output self-test data for performing access operations to confirm correct operation of the functional unit memory. A debug controller outputs debug data and co-ordinates debug operations, the debug controller being one of the plurality of functional units.