Abstract: A device includes a processor and memory. The memory has stored thereon a plurality of executable instructions. The executable instructions, when executed by the processor, cause the processor to: receive an access request affecting an operation of the device; facilitate encryption and/or authentication across an interface coupled to the device, wherein the interface is configured to secure the access request; and execute the access request.

Abstract: A slave device communicates with a host system via a host communications bus. The host system includes one processing unit that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processing unit and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the “internal” physical address of the slave's resources and forwards the access to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request.

Abstract: A graphics processor includes a graphics object list building unit that determines the location of each draw call in a scene to be rendered and generates a list of draw calls for each sub-region (tile) that the scene to be rendered is divided into. The draw call lists are stored in a memory. A graphics object selection unit of a renderer of the graphics processor then determines which draw call is to be rendered next by considering the draw call list stored in the memory for the sub-region (tile) of the scene that is currently being rendered.

Abstract: A microprocessor pipeline arrangement 1 includes a plurality of functional units 2, 3, 4, 5 and 6. Each functional unit 2, 3, 4, 5, 6 also has access to a respective cache memory 7, 8, 9, 10, 11. Threads for processing are received by the first functional unit 2 from an external source 12, and output by an end functional unit 6 of the pipeline to an output target 13. If a thread encounters a cache-miss on its passage through the pipeline, the thread is allowed to continue to pass through the pipeline in the normal manner. However, when the thread reaches the end of the pipeline, it is sent via a loopback path 14 back to the beginning of the pipeline to be sent through the pipeline again. In this way, any thread that has not completed its processing on passing through the pipeline can be sent through the pipeline again to allow the processing of the thread to be completed.

Abstract: A microprocessor pipeline arrangement 1 includes a plurality of functional units P1, P2, P3, . . . , PN. A number of the functional units P1, P3, PN have access to a respective cache memory C1, C3, CN from which it can retrieve data needed to process threads that pass through the pipeline. The pipeline arrangement 1 also includes a number of monitors to determine when the system enters a state of livelock (e.g. inter-cache livelocks, intra-cache livelocks and/or “near-livelock” situations): a top-level monitor MT to detect livelock situations in the pipeline as a whole; and second-level (“local”) monitors M1 and M3 associated with individual caches C1 and C3. If the system is determined to have entered a livelock state, e.g. by the top-level monitor MT, the number of threads able to change the contents of one or more of the caches C1, C3, CN is reduced.

Abstract: A 3D graphics rendering pipeline is used to carry out data comparisons for motion estimation in video data encoding. Video data for the pixel block of the video frame currently being encoded is loaded into the output buffers of the rendering pipeline. The video data for the comparison pixel blocks from the reference video frame is stored as texture map values in the texture cache of the rendering pipeline. Once the sets of pixel data for comparison have been stored, the rendering pipeline is controlled to render a primitive having fragment positions and texture coordinates corresponding to the data values that it is desired to compare. As each fragment is rendered, the stored and rendered fragment data is compared by fragment compare unit and the determined differences in the data values are accumulated in an error term register.

Abstract: A graphic rendering pipeline has a number of different rendering units and receives fragments for rendering. A renderer stated word cache is used to store rendering state data to be used to configure the rendering units when they render a fragment. Each rendering unit includes a functional block which carries out a rendering operation on a received fragment and a renderer state word interface that can be used to look up the required rendering state data from the renderer state word cache. Each fragment is provided to the rendering pipeline with fragment data that indicates, inter alia, a fragment index, a renderer state word index, and other fragment data that is necessary to render the fragment. When a rendering unit of the rendering pipeline receives a fragment to be rendered, it firstly uses the renderer state word index associated with the fragment to look-up, using its renderer state word interface, the relevant rendering state data from the renderer state word cache.

Abstract: A slave device (20) communicates with a host system (21) via a host communications bus (22). The host system (21) includes one (or more) processing units that can act as bus masters and send access requests for slave resources on the slave device (20) via the communications bus (22). The slave device platform (20) includes a memory management unit (23), a programmable central processing unit (24) and one or more slave resources (25). The memory management unit (23) acts as an address translating device, and accepts requests with virtual addresses from the master device or devices on the host system (21), translates the virtual addresses used in the access requests to the “internal” physical addresses of the slave's resources and forwards the accesses of the appropriate physical resources (25).

Abstract: An array of texture data elements (texels) is subdivided into a plurality of 8×4 texture element blocks, each of which 8×4 texture element blocks encodes two 4×4 texture element sub-blocks 3, 4. Each encoded texture data block includes data indicating a method to be used to generate a set of color values to be used for the texture elements that the encoded data block represents, and data indicating a method to be used for generating the colors of the individual texture elements using that generated set of colors. As well as the individual texture data blocks, a header data block encoding a base set of colors is generated. This base color set defines a set of colors that is used to generate the colors to be used when reproducing each individual encoded texture data block.

Abstract: A memory management arrangement includes a memory management unit, a cache memory and a queue arrangement. The queue is a first-in, first-out (FIFO) buffer which can queue failed memory access requests and return them as inputs to the memory management unit via the bus 5 for retrying through the memory management unit at a later time. If a memory access request sent to the memory management unit experiences a cache “miss”, instead of blocking memory access requests until the required address data has been loaded into the cache, the memory management unit operates to place the failed memory access request in the replay queue, and allows subsequent memory access requests to continue. The failed memory access requests in the queue are then continuously circulated through the memory management unit from the queue alternately with new memory access requests from other access initiators.

Abstract: A graphics processing platform includes a rasteriser 50 that receives primitives representing an image to be displayed for processing. The rasteriser 50 determines which sets of sampling points of the image include sampling points that are covered by a given primitive, and then generates a fragment for rendering for each set of sampling points found to include a sampling point that is covered by the primitive and passes those fragments to a renderer 51 for rendering. The renderer 51 carries out rendering operations on the fragments that it receives, and stores the rendered fragment data in tile buffers 52. The rendered fragment data is stored in multiple copies in the appropriate sample positions in the tile buffers 52, so as to provide a separate set of fragment data for each individual sample position taken of the image. The data from the tile buffers 52 is input to a downsampling unit 53, and hence output to a frame buffer 54 of a display device 55 for display.

Abstract: A 3D graphics rendering pipeline is used to carry out data comparisons for motion estimation in video data encoding. Video data for the pixel block of the video frame currently being encoded is loaded into the output buffers of the rendering pipeline. The video data for the comparison pixel blocks from the reference video frame is stored as texture map values in the texture cache of the rendering pipeline. Once the sets of pixel data for comparison have been stored, the rendering pipeline is controlled to render a primitive having fragment positions and texture coordinates corresponding to the data values that it is desired to compare. As each fragment is rendered, the stored and rendered fragment data is compared by fragment compare unit and the determined differences in the data values are accumulated in an error term register.

Abstract: An array of texture data elements (texels) is subdivided into a plurality of 8×4 texture element blocks, each of which 8×4 texture element blocks encodes two 4×4 texture element sub-blocks 3, 4. Each encoded texture data block includes data indicating a method to be used to generate a set of colour values to be used for the texture elements that the encoded data block represents, and data indicating a method to be used for generating the colours of the individual texture elements using that generated set of colours. As well as the individual texture data blocks, a header data block encoding a base set of colours is generated. This base colour set defines a set of colours that is used to generate the colours to be used when reproducing each individual encoded texture data block.

Abstract: In a graphics processing system, the left, right, top and bottom edge planes for the purposes of clipping are set to the maximum values that can be represented using floating-point format numbers, vertex positions are snapped to a grid of predefined vertex positions, and the precision of selected vertices is prioritized when deriving edge functions for a given primitive. In respect of the depth near and far clipping planes, those planes are set to the maximum floating-point number format that can be represented for “Z” in the graphics system, but then fragments that have a Z value that falls outside the range zero to one are discarded using a depth test. In respect of the eye-plane, the need for clipping is avoided by modifying edge equations generated for a primitive in dependence on the sign of a “W” value for each vertex of the primitive.

Abstract: A 3D graphics rendering pipeline is used to carry out data comparisons for motion estimation in video data encoding. Video data for the pixel block of the video frame currently being encoded is loaded into the output buffers of the rendering pipeline. The video data for the comparison pixel blocks from the reference video frame is stored as texture map values in the texture cache of the rendering pipeline. Once the sets of pixel data for comparison have been stored, the rendering pipeline is controlled to render a primitive having fragment positions and texture coordinates corresponding to the data values that it is desired to compare. As each fragment is rendered, the stored and rendered fragment data is compared by fragment compare unit and the determined differences in the data values are accumulated in an error term register.

Abstract: An array of texture data elements (texels) is subdivided into a plurality of 8×4 texture element blocks, each of which 8×4 texture element blocks encodes two 4×4 texture element sub-blocks 3, 4. Each encoded texture data block includes data indicating a method to be used to generate a set of color values to be used for the texture elements that the encoded data block represents, and data indicating a method to be used for generating the colors of the individual texture elements using that generated set of colors. As well as the individual texture data blocks, a header data block encoding a base set of colors is generated. This base color set defines a set of colors that is used to generate the colors to be used when reproducing each individual encoded texture data block.

Abstract: When an alpha test is performed as part of the rendering process in a multisampled graphics processing pipeline, rather than taking the single alpha value initially defined for each fragment an individual alpha value is generated in respect of each of covered sampling position that the fragment in question is being used to render. The individual alpha values estimated for each sample position are then individually compared with a threshold alpha value defined for the alpha test, and the result of this alpha test comparison is used to decide either keep or discard the sample position from further processing.

Abstract: A graphics processing platform includes a rasteriser 50 that receives primitives representing an image to be displayed for processing. The rasteriser 50 determines which sets of sampling points of the image include sampling points that are covered by a given primitive, and then generates a fragment for rendering for each set of sampling points found to include a sampling point that is covered by the primitive and passes those fragments to a renderer 51 for rendering. The renderer 51 carries out rendering operations on the fragments that it receives, and stores the rendered fragment data in tile buffers 52. The rendered fragment data is stored in multiple copies in the appropriate sample positions in the tile buffers 52, so as to provide a separate set of fragment data for each individual sample position taken of the image. The data from the tile buffers 52 is input to a downsampling unit 53, and thence output to a frame buffer 54 of a display device 55 for display.

Abstract: A graphics processing platform includes a rasteriser 50 that receives primitives representing an image to be displayed for processing. The rasteriser 50 determines which sets of sampling points of the image include sampling points that are covered by a given primitive, and then generates a fragment for rendering for each set of sampling points found to include a sampling point that is covered by the primitive and passes those fragments to a renderer 51 for rendering. The renderer 51 carries out rendering operations on the fragments that it receives, and stores the rendered fragment data in tile buffers 52. The rendered fragment data is stored in multiple copies in the appropriate sample positions in the tile buffers 52, so as to provide a separate set of fragment data for each individual sample position taken of the image. The data from the tile buffers 52 is input to a downsampling unit 53, and thence output to a frame buffer 54 of a display device 55 for display.

Abstract: A memory management arrangement includes a memory management unit 1, a cache memory 2 and a queue arrangement 3. The queue 3 is a first-in, first-out (FIFO) buffer which can queue failed memory access requests and return them as inputs to the memory management unit 1 via the bus 5 for retrying through the memory management unit at a later time. If a memory access request sent to the memory management unit 1 experiences a cache “miss”, instead of blocking memory access requests until the required address data has been loaded into the cache 2, the memory management unit 1 operates to place the failed memory access request in the replay queue 3, and allows subsequent memory access requests to continue. The failed memory access requests in the queue 3 are then continuously circulated through the memory management unit 1 from the queue alternately with new memory access requests from other access initiators 4.