Abstract: A gate drive supply circuit generating a high-level supply voltage and a low-level supply voltage for driving N-type high-side and low-side power MOSFETs in a multiple-output, low-voltage DC-DC converter integrated circuit. The gate drive supply circuit includes a boost regulator for generating the low-level supply voltage and a charge pump doubler for generating the high-level supply voltage. Both the high-level supply voltage and the low-level supply voltage are distributed to one or more regulators, including but not limited to buck or boost type regulators.
Abstract: A power converter including a first stage, a reservoir capacitor and a second stage. The first stage converts the voltage of a primary energy source, such as a battery, to a voltage on the reservoir capacitor, which stores a large amount of energy in the form of a voltage substantially larger than the voltage of the primary energy source. The second stage converts the voltage on the reservoir capacitor to a substantially constant voltage for a load device that demands current having the form of large, short, current pulses. The cascaded converter prevents the pulsating load currents of the load device, such as a GSM power amplifier, from causing a severe voltage loss at the battery. This increases the power available from the battery and reduces loses from the internal resistance of the battery.
Type:
Grant
Filed:
October 15, 2002
Date of Patent:
September 28, 2004
Assignee:
Arques Technology, Inc.
Inventors:
Kwang H. Liu, Sorin L. Negru, Fu-Yuan Shih, George Hsieh
Abstract: A voltage regulator for providing a bidirectional current and a regulated voltage to a load. The voltage regulator regulates the output voltage at one half the level of the input voltage using a voltage doubler circuit in reverse. The regulator provides current to the load when the output voltage drops and receives current from the load when the output voltage rises. The voltage regulator is particularly suited to supplying a termination voltage to multiple line drivers in a DDR DRAM system, where the line drives require an active termination voltage to reduce power. Additionally, a pair of linear regulators, one for clamping the output voltage at a predetermined low voltage level and for supplying additional current demanded by the load, and the other for clamping the output voltage at a predetermined high voltage level and for receiving additional current supplied by the load, is included.
Type:
Grant
Filed:
September 9, 2002
Date of Patent:
March 16, 2004
Assignee:
Arques Technology, Inc.
Inventors:
Kwang H. Liu, Sorin L. Negru, Fu-Yuan Shih