Patents Assigned to Arteris
  • Patent number: 8254380
    Abstract: The system for managing messages transmitted in an interconnect network connecting blocks on a chip comprises agents linked by point-to-point links able to transmit, by static routing, messages comprising a priority information item quantified on N levels. The system comprises at least one agent initiating request messages to at least one recipient agent. A request message comprises a header and, where appropriate, content data. The system comprises means of generating a priority message, to a recipient agent, to which at least on request message has previously been transmitted with no response message received in return.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: August 28, 2012
    Assignee: Arteris
    Inventors: Philippe Boucard, Vincent Vacquerie
  • Patent number: 8031730
    Abstract: Method for transmitting a sequence of messages in a point-to-point interconnection network comprising message initiating agents, message destination agents and message transmission agents. During a transmission of an indivisible sequence of messages from an initiating agent to a destination agent, an output of a message transmission agent is locked onto an input of the transmission agent, the other inputs of the said transmission agent being able to transmit messages to the other outputs of the said transmission agent.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: October 4, 2011
    Assignee: Arteris
    Inventors: César Douady, Philippe Boucard
  • Publication number: 20100296400
    Abstract: Method of managing priority during the transmission of a message, in an interconnections network comprising at least one transmission agent which comprises at least one input and at least one output, each input comprising a means of storage organized as a queue of messages. A message priority is assigned during the creation of the message, and a queue priority equal to the maximum of the priorities of the messages of the queue is assigned to at least one queue of messages of an input. A link priority is assigned to a link linking an output of a first transmission agent to an input of a second transmission agent, equal to the maximum of the priorities of the queues of messages of the inputs of said first agent comprising a first message destined for that output of said first agent which is coupled to said link, and the priority of the link is transmitted to that input of said second agent which is coupled to the link.
    Type: Application
    Filed: August 2, 2010
    Publication date: November 25, 2010
    Applicant: ARTERIS
    Inventors: Cesar Douady, Philippe Boucard
  • Patent number: 7769027
    Abstract: Method of managing priority during the transmission of a message, in an interconnections network comprising at least one transmission agent which comprises at least one input and at least one output, each input comprising a means of storage organized as a queue of messages. A message priority is assigned during the creation of the message, and a queue priority equal to the maximum of the priorities of the messages of the queue is assigned to at least one queue of messages of an input. A link priority is assigned to a link linking an output of a first transmission agent to an input of a second transmission agent, equal to the maximum of the priorities of the queues of messages of the inputs of said first agent comprising a first message destined for that output of said first agent which is coupled to said link, and the priority of the link is transmitted to that input of said second agent which is coupled to the link.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: August 3, 2010
    Assignee: Arteris
    Inventors: Cesar Douady, Philippe Boucard
  • Patent number: 7755920
    Abstract: An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and the sequencer, said request manager includes an input queue for storing the high level memory access requests and an arbitration function which takes account of the data of the cache and the data of the input queue to designate a request which is to be executed, thus allowing the memory bank, the sequencer and the request manager to be provided on a single chip, the physical interface providing the connection of the chip with the outside.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: July 13, 2010
    Assignee: Arteris
    Inventors: Philippe Boucard, Pascal Godet, Luc Montperrus
  • Publication number: 20100122004
    Abstract: The message switching system comprises at least two inputs and at least one output, first arbitration means dedicated to said output, and management means designed to determine a relative order OR(i,j) of one input relative to the other, for any pair of separate inputs belonging to the system and having sent requests for the assignment of said output, and designed to assign said output. Said management means comprise storage means designed to store said relative orders OR(i,j), initialization means designed to initialize said relative orders OR(i,j) such that only one of said inputs takes priority on initialization, and updating means designed to update all of said relative orders when a new request arrives at said first arbitration means, or when said output is assigned to one of said inputs.
    Type: Application
    Filed: November 11, 2009
    Publication date: May 13, 2010
    Applicant: ARTERIS
    Inventors: Philippe Boucard, Luc Montperrus
  • Patent number: 7639704
    Abstract: The message switching system (51) comprises at least two inputs (52, 53, 54, 55) and at least one output (56), first arbitration means (62) dedicated to said output (56), and management means (64) designed to determine a relative order OR(i,j) of one input relative to the other, for any pair of separate inputs belonging to the system (51) and having sent requests for the assignment of said output (56), and designed to assign said output (56). Said management means (64) comprise storage means (70) designed to store said relative orders OR(i,j), initialization means (66) designed to initialize said relative orders OR(i,j) such that only one of said inputs takes priority on initialization, and updating means (68) designed to update all of said relative orders when a new request arrives at said first arbitration means (62), or when said output is assigned to one of said inputs.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: December 29, 2009
    Assignee: Arteris
    Inventors: Philippe Boucard, Luc Montperrus
  • Patent number: 7574629
    Abstract: In some embodiments, a system for communication between agents in a point-to-point interconnection system includes at least one initiator agent capable of dispatching at least one message destined for at least one determined receiver agent; at least one intermediate agent capable of forwarding at least one message to at least one determined receiver agent; at least one receiver agent capable of receiving at least one message originating from an initiator agent via at least one intermediate agent; and means of error detection and means of erroneous message marking. In some embodiments, a receiver agent includes means for formulating an error message and means for sending the error message to the initiator agent so as to warn the said initiator agent of the presence of an error.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: August 11, 2009
    Assignee: Arteris
    Inventors: César Douady, Philippe Boucard
  • Publication number: 20090080280
    Abstract: An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and the sequencer, said request manager includes an input queue for storing the high level memory access requests and an arbitration function which takes account of the data of the cache and the data of the input queue to designate a request which is to be executed, thus allowing the memory bank, the sequencer and the request manager to be provided on a single chip, the physical interface providing the connection of the chip with the outside.
    Type: Application
    Filed: September 25, 2008
    Publication date: March 26, 2009
    Applicant: Arteris
    Inventors: Philippe Boucard, Pascal Godet, Luc Montperrus
  • Patent number: 7148728
    Abstract: Digitally controlled delay device, including a plurality of fine delay elements and a plurality of coarse delay elements, capable of delaying a signal generated by the device, by a fine or coarse delay respectively, the fine delay elements having delay times of between 60 and 170% of the mean of the fine delays and the sum of the fine delay times being greater than or equal to at least one coarse delay.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: December 12, 2006
    Assignee: Arteris
    Inventors: Luc Montperrus, Philippe Boucard, Jean-Jacques Lecler
  • Publication number: 20040225490
    Abstract: Device for emulating one or more integrated-circuit chips comprising electronic cards connected together via a communication bus, said electronic cards possessing programmable emulation units. The emulation device includes configurable point-to-point links and, the chip or chips including multisynchronous modules and at least one asynchronous message communication management module, a module is modeled by at most one programmable emulation unit.
    Type: Application
    Filed: November 10, 2003
    Publication date: November 11, 2004
    Applicant: ARTERIS
    Inventors: Cesar Douady, Philippe Boucard