Abstract: In accordance with the various aspects and embodiment of the invention, a system and method are disclosed that automate the process of generating protocol converters using machine-readable descriptions of the external hardware components interfaces and the associated protocol. One advantage of the invention is lowered mistakes in generating the protocol converters. Another advantage is increased productivity when designing the interconnect, such as a network-on-chip (NoC) interconnect used in a system-on-chip (SoC).

Abstract: System and methods are disclosed that are implemented by a tool for generation and synthesis of networks, such as a network-on-chip (NoC). The tool receives input from the user, either as a data file or through input in a graphical user interface (display). The tool generates a NoC from a set of physical constraints and performance constraints. The tool produces the NoC with all its elements, which is a legal and meets the constraints. The tool also receives as an input performance scenarios or performance requirement that can be used to transform an existing topology to satisfy the newly added requirements. The tool identifies and reuses switches to reduce the number of switches. The resulting output represents the network, such as the NoC, that meets the requirements.

Abstract: System and methods are disclosed that are implemented by a tool for generation and synthesis of networks, such as a network-on-chip (NoC). The tool receives input from the user, either as a data file or through input in a graphical user interface (display). The tool generates a NoC from a set of physical constraints and performance constraints. The tool produces the NoC with all its elements, which is a legal and meets the constraints. The tool also receives as an input performance scenarios or performance requirement that can be used to transform an existing topology to satisfy the newly added requirements. The resulting output represents the network, such as the NoC, that meets the requirements.

Abstract: A cache coherent interconnect connected to one or more agents, such as CPUs, GPUS, Peripherals, etc. using network interface units (NIUs), and having one or more internal modules, such as a directory, is provided with one or more event-to-message converters, and one or more message-to-event converters. When a particular event occurs within one of the agents or modules, a message is initiated and transmitted using the existing interconnect wiring to one or more agents or modules, which have associated NIUs, that need to be aware of the event. Response messages showing the status of the event-message may also be generated. Therefore, messages are sent when events occur, instead of constantly using bandwidth for status updates when no status is changing, making the interconnect more efficient and freeing up bandwidth. These converters are provided as additional hardware blocks incorporated into the various NIUs and modules.

Abstract: A network-on-chip (NoC) provides packet-based communication between a plurality of initiator computing elements and a plurality of target computing elements. The NoC includes a plurality of observer processors upstream of and corresponding to the target computing elements. Each observer processor is configured to perform packet inspection and generate information in real-time about traffic load on its corresponding target computing element. An aggregator processor is configured to process the traffic load information from the observer processors to identify those target computing elements that are most heavily contended.

Abstract: Systems and methods are disclosed for synthesis of a network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC description from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting network description output includes placement of elements on a floorplan of a chip that represents the network, such as the NoC.

Abstract: A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP. The system generated data for training and testing the model by treating the logical parameters and physical parameters subset as one for the IP block. The system digitizes the non-numerical parameters and compresses timing arcs. The system uses the trained model to characteristic behavior for an IP block directly from the combined vector of logical parameter values and physical parameter values.

Abstract: Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.

Abstract: A system and method implemented by tool is disclosed. The tool receives input of a network-on-chip (NoC) and the NoC's desired connectivity and efficiently guides the designer through interactive NoC topology editing sessions to ensure the obtained network is both complete and correct during topology creation or modification.

Abstract: A tool is disclosed for using custom subnetwork description during generation and synthesis of the network, such as a network-on-chip (NoC). The tool allows for incremental synthesis and transformation of a deadlock-free NoC. The NoC topology is translated into an existing segment; reusing the existing segment in a new route and generating the deadlock-free NoC topology. The tool includes a machine learning model that is trained for synthesis and generation of the NoC and is capable of providing incremental synthesis. The model can also receive feedback from past or previous synthesis for further training of the model.

Abstract: Generation of a full register-transfer level (RTL) description of an electronics system includes generating an optimized pipeline configuration from inputs including a database of RTL elements, and a list of configurable pipeline components; and generating the full RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for a configuration that optimizes area and timing.

Abstract: A network-on-chip (NoC) provides packet-based communication between a plurality of initiator computing elements and a plurality of target computing elements. The NoC includes a plurality of observer processors upstream of and corresponding to the target computing elements. Each observer processor is configured to perform packet inspection and generate information in real-time about traffic load on its corresponding target computing element. An aggregator processor is configured to process the traffic load information from the observer processors to identify those target computing elements that are most heavily contended.

Abstract: A cache coherent interconnect connected to one or more agents, such as CPUs, GPUs, Peripherals, etc. using network interface units (NIUs), and having one or more internal modules, such as a directory, is provided with one or more event-to-message converters, and one or more message-to-event converters. When a particular event occurs within one of the agents or modules, a message is initiated and transmitted using the existing interconnect wiring to one or more agents or modules, which have associated NIUs, that need to be aware of the event. Response messages showing the status of the event-message may also be generated. Therefore, messages are sent when events occur, instead of constantly using bandwidth for status updates when no status is changing, making the interconnect more efficient and freeing up bandwidth. These converters are provided as additional hardware blocks incorporated into the various NIUs and modules.

Abstract: Floorplanning for a semiconductor chip includes loading an image of a first floorplan of the chip; converting the digital image to a grayscale image; detecting blockages in the grayscale image; and generating a second floorplan corresponding to the first floorplan. The second floorplan shows representations of the blockages and maximum available area for a network-on-chip (NoC).

Abstract: System and methods are disclosed for physical implementation guidance for very fast rectilinear routing of wires in a floorplan related to a network-on-chip (NoC). The system generates physical implementation guidance, which is during physical implementation of the synthesized NoC.

Abstract: A tool is disclosed that automatically generates constraints for the placement of network elements, which can be understood by the backend tools that follow the constraints. The tool also constrains the placement within given bounds results in faster runtimes in the backend tools. Further, the tool automatically inserts additional elements into the topology to help with timing closure in downstream or backend tools. Additionally, the tool provides real-time feedback on wire congestion to the user during editing. The tool also implements a machine learning model that is trained and receives feedback for solutions provided to further train the model. The tool also includes the ability to use feedback to train a machine learning model for automated and assisted topology analysis and synthesis. The tool generates physical implementation guidance, which is during physical implementation of the synthesized NoC.

Abstract: A tool is disclosed for physical implementation guidance that allows interactive compute a legal and optimization placement of an existing topology on a floorplan. The tool can be invoked multiple times during topology editing. The tool also includes the ability to use feedback to train a machine learning model for automated and assisted topology analysis and synthesis. The tool generates physical implementation guidance, which is during physical implementation of the synthesized NoC.

Abstract: A broadcast adapter in a network-on-chip (NoC) is used for broadcasting transactions in the form of packets from an initiator to multiple targets and for receiving responses from the targets that are combined and sent to the initiator. The transactions originate from an initiator and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the initiator. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple targets. The targets send a response, which is transported back by the NoC to the corresponding initiator.

Abstract: A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.

Abstract: System and methods are disclosed for augmenting a synthesized NoC, with data that guides a physical implementation of the NoC topology in a way that coincides with the topology synthesis result and reduces timing violations in the final physical design. The system generates physical implementation guidance, which is during physical implementation of the synthesized NoC. The system inserts a link as a pipeline placeholder and a minimum set of created module regions are assigned to a specific link of the topology. Each route has a new link and corresponding module region inserted into the physical path.