Abstract: Systems-on-chip are designed with different IPs that use different data protection schemes. Modules are used between the IPs, and the modules convert between protection schemes. Protection schemes can be per-byte, word, packet, flit, or burst. Conversion can involve splitting, merging, encapsulation, conversion, and generation of redundant information. Encoding of redundancy according to protection schemes can occur directly at an IP interface or within an interconnect, such as within a packet-based NoC. Designs include SoCs, hardware description language code describing functions within SoCs, and non-transient computer readable media that store such source code.

Abstract: A NoC topology is represented on top of a physical view of a chip's floorplan. The NoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of switches within the floorplan is automatically computed. Locations can also be edited by a user. Statistical metrics are calculated, including wire length, switch area, NoC area, and maximum signal propagation delay for logic in each of multiple clock domains. Wire density can also be overlaid on chip's floorplan on the display. The NoC topology is represented by a data structure indicating connections between initiator and target endpoints with ordered lists of switches in between. The data structures are written and read from memory or a non-transient computer readable medium. The locations of endpoint and switches are also written out, as scripts for place & route tools.

Abstract: A system and method are disclosed for multiple coherent caches supporting agents that use different, incompatible coherence models. Compatibility is implemented by translators that accept coherency requests and snoop responses from an agent and accept snoop requests and coherency responses from a coherence controller. The translators issue corresponding coherency requests and snoop responses to the coherence controller and issue corresponding coherency responses and snoop requests to the agent. Interaction between translators and the coherence controller accord with a generic coherence model, which may be a subset, superset, or partially inclusive of features of any native coherence model. A generic coherence protocol may include binary values for each of characteristics: valid or invalid, owned or non-owned, unique or shared, and clean or dirty.

Abstract: Compression of address bits within a cache coherent subsystem of a chip is performed, enabling a cache coherent subsystem to avoid transmitting, storing, and operating upon unnecessary address information. Compression is performed according to any appropriate lossless algorithm, such as discarding of bits or code book lookup. The algorithm may be chosen according to constraints on logic delay and silicon area. An algorithm for minimum area would use a number of bits equal to the rounded up binary logarithm of the sum of all addresses of all memory regions. A configuration tool generates a logic description of the compression algorithm. The algorithm may be chosen automatically by the configuration tool. Decompression may be performed on addresses exiting the coherent subsystem.

Abstract: A system and method of defining the topology of a network-on-chip. The IP sockets and their data transfer connectivity are defined. The location of each IP socket is defined. A number of switches are defined so that there is at least one switch within a distance from each IP socket, the distance being less than that over which a signal propagates within one clock cycle period. The switches are coupled by links. Links may comprise pipeline stages, storage buffers, and are characterized by a data width.

Abstract: Method of managing priority during the transmission of a message, in an interconnections network comprising at least one transmission agent which comprises at least one input and at least one output, each input comprising a means of storage organized as a queue of messages. A message priority is assigned during the creation of the message, and a queue priority equal to the maximum of the priorities of the messages of the queue is assigned to at least one queue of messages of an input. A link priority is assigned to a link linking an output of a first transmission agent to an input of a second transmission agent, equal to the maximum of the priorities of the queues of messages of the inputs of said first agent comprising a first message destined for that output of said first agent which is coupled to said link, and the priority of the link is transmitted to that input of said second agent which is coupled to the link.