Abstract: An analog-to-digital converter (ADC) device equipped with a conversion suspension function and an associated operation method thereof are provided. The ADC device includes: an interleaved clock controller, arranged to generate a first clock signal and a second clock signal according to a master clock signal; and a multi-ADC circuit, coupled to the interleaved clock controller, arranged to perform analog-to-digital conversion. The multi-ADC circuit includes a first ADC and a second ADC, wherein the first ADC performs sampling and conversion operations according to the first clock signal, and the second ADC performs sampling and conversion operations according to the second clock signal. Based on the timing control of the first clock signal and the second clock signal, when any ADC of the first ADC and the second ADC is performing a sampling operation, the other ADC of the first ADC and the second ADC suspends conversion.

Abstract: A voltage divider circuit regarding a battery voltage and an associated electronic device equipped with the voltage divider circuit are provided. The voltage divider circuit may include a first level shifter circuit, a second level shifter circuit and a controlled voltage divider. The first level shifter circuit selectively performs a first level shifting operation on an original enable signal according to respective voltage levels of multiple control signals to generate a first enable signal. The second level shifter circuit selectively performs a second level shifting operation on the first enable signal according to a voltage level of the first enable signal to generate a second enable signal. The controlled voltage divider selectively performs a voltage dividing operation on the battery voltage according to a voltage level of the second enable signal to generate a divided voltage of the battery voltage to be an output of the voltage divider circuit.

Abstract: The present invention discloses a hysteresis comparator comprising an input stage, a hysteresis current generating circuit and an output stage. In the operation of the hysteresis comparator, the input stage is configured to receive a pair of differential input signals to generate at least one differential current signal; the hysteresis current generating circuit is configured to generate at least one hysteresis current to adjust the differential current signal to generate an adjusted differential current signal, wherein the hysteresis current generating circuit includes a common mode voltage detecting circuit for detecting a common mode voltage of the differential input signal for generating the hysteresis current; and the output stage is configured to generate an output signal according to the adjusted differential current signal.

Abstract: A delay circuit and an electronic system equipped with the delay circuit are provided. The delay circuit includes an input terminal, an output terminal, a bias current generator and a delay generator. The bias current generator is coupled between a first reference voltage and a second reference voltage, and is configured to generate a bias current. The delay generator is coupled between the first reference voltage and the second reference voltage, and is configured to generate a delay of the delay signal relative to the input signal according to the bias current. The bias current generator includes a current mirror, a current module and a transistor. The delay generator includes a first current mirror sub-circuit, a second current mirror sub-circuit, a transistor, a capacitor, a switch circuit and a Schmitt inverter, wherein the output terminal is coupled to the Schmitt inverter to output the delay signal.

Abstract: A clock fail detector is provided. The clock fail detector includes a timing control signal generator and a clock fail detection module, which may generate control signals according to a clock signal and perform clock fail detection according to the control signals, respectively. The clock fail detection module may comprise first integrators, sample and hold circuits, a second integrator and a comparator. The first integrator may convert previous periods of the clock signal into reference voltages according to ping pong mode control signals within the control signals, respectively. The sample and hold circuits may sample and hold the reference voltages according to the ping pong mode control signals. The second integrator may convert a current clock period of the clock signal into a ramp signal. The comparator may compare the ramp signal with a reference voltage to generate a comparison result signal for indicating whether the clock signal is normal.

Abstract: A comparator circuit includes: a comparator, coupled between a power voltage and a ground voltage, configured to perform a comparison according to a set of input signals to generate a comparison signal; a current source; and positive feedback circuits. The comparator circuit includes a set of input terminals and sets of transistors respectively coupled between a power voltage and a node or a ground voltage. The positive feedback circuits perform positive feedback operations on the node to generate instant currents on the node, to make the comparator switch the comparison signal in response to transition of the set of input signals in real time. Any of the positive feedback circuits includes: a first switch, configured to enable or disable said any positive feedback circuit in response to transition of the comparison signal; and a set of transistors, configured to generate a second current corresponding to the first current.

Abstract: A crystal oscillator control circuit includes a first terminal and a second terminal, a current source, and a peak detection and bias voltage adjustment circuit. The first terminal and the second terminal are arranged to couple the crystal oscillator control circuit to a crystal. The current source is coupled to a power supply voltage and generates a bias current. The peak detection and bias voltage adjustment circuit is coupled between the bias current and a ground voltage and coupled to the first terminal, and performs peak detection and bias voltage adjustment to correspondingly generate a first signal at a node. The low-pass filter low-pass filters the first signal to generate a filtered signal. The feedback control circuit is arranged to perform feedback control according to the filtered signal to generate an oscillation signal at one or both of the first terminal and the second terminal.

Abstract: The present invention provides an oscillator circuit and associated oscillator device. The oscillator circuit comprises a negative-temperature-coefficient (NTC) bias current generating circuit and a set of oscillator sub-block circuits. The NTC bias current generating circuit is coupled between a supply voltage and a ground voltage, and is arranged to generate at least one NTC bias current. The set of oscillator sub-block circuits are coupled to each other to form an oscillator. Each oscillator sub-block circuit of the set of oscillator sub-block circuits comprises a plurality of transistors coupled between the supply voltage and a node within the NTC bias current generating circuit, wherein the NTC bias current generating circuit and the aforementioned each oscillator sub-block circuit share at least one transistor in the plurality of transistors.

Abstract: A power-on reset circuit arranged to generate a reset signal according to a power supply voltage includes: a power supply voltage detector, a holding circuit, a reference voltage generator and a reset determination circuit. The power supply voltage detector is controllable by the reset signal, and arranged to detect a level of the power supply voltage to generate a detection signal. The holding circuit is arranged to output an enablement signal according to the detection signal, wherein the holding circuit selectively maintains a level of the enablement signal according to a level of the detection signal. The reference voltage generator is controllable by the enablement signal to selectively output a reference voltage. The reset determination circuit is arranged to output the reset signal according to the power supply voltage and the reference voltage.

Abstract: A dynamic bias current generator includes a detection circuit and at least one current generating circuit. The detection circuit is used for generating a detection signal, and includes: current source coupled to the power supply voltage; a first set of transistors coupled between the current source and the ground voltage; a second set of transistors coupled between the power supply voltage and the ground voltage; a first capacitor coupled to the power supply voltage; and a second capacitor coupled to the ground voltage. The at least one current generating circuit is used for generating dynamic bias current according to the detection signal, and includes multiple transistors and a terminal for outputting voltage signal corresponding the dynamic bias current. The dynamic bias current may be used to increase the reaction speed of the comparator and may be used in a power down detection circuit.