Abstract: An internal net of a digital circuit is virtually probed while performing a dynamic functional stimulation that includes changing vectors asserted to a dynamic functional interface. A JTAG SAMPLE command is triggered through a JTAG interface at a timing during the dynamic functional stimulation by controlling the timing of a JTAG TCK rising clock edge. Captured JTAG SAMPLE data is shifted out to the JTAG interface. The JTAG SAMPLE data, which includes the logic states of internal nets at a chosen timing during the dynamic functional stimulation, are stored. A sequence database is built by repeating the test with incrementally different JTAG rising clock edge timings.