Abstract: A digital self-calibrating delay line is disclosed wherein in a chain of individual but identical time delay elements a calibrated signal running therethrough is compared with the subsequent input signal on each of the individual time delay elements until a coincidence time delay element is determined at which time an output is indicated. The period of the calibrating signal is chosen to be equal to the delay to be imparted to a signal to be delayed. Prior to or upon the appearance of the signal to be delayed, the calibration signal is removed and the incoming signal inserted into the time delay chain to output at the individual time delay element determined by the calibration signal. In an alternate embodiment, by the addition of a few components to each of the time delay elements, the subject invention is interconnected to output a signal whose frequency is a multiple of the input signal.

Abstract: A circuit to selectively process dip switches onto bus lines in a computer or device utilizing digital logic circuits wherein the dip switches are operably connected to a changeable source of digital signals so that upon command at desired times, the output of the dip switches connected to the bus lines may be reversed. Such a circuit consists of connecting the dip switches on one side to the bus lines and the other side through a current limiting resistor to the output of a logic circuit such as a NAND gate or other circuit which constantly outputs a digital signal. The input then to this logic circuit may be changed as desired to reverse the logic circuit output and thus the output of the dip switches. If desired, in place of the NAND gate output, the current limiting resistor may be grounded or connected to digital "1" in which case a constant digital signal is outputted to the bus lines upon dip switch closure.