Abstract: Various structures and fabrication methods for leadless plastic chip carrier (QFN) packages which utilize carriers in strip format, wherein the leads (or terminals) are formed to be electrically isolated from one another within each unit and in which the units are formed to be electrically isolated from one another within the strip using chemical etching techniques.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bonding the semiconductor die to ones of the contact pads; releasably clamping the leadframe strip in a mold by releasably clamping the contact pads; molding in a molding compound to cover the semiconductor die, the wire bonds and a portion of the contact pads not covered by the clamping; releasing the leadframe strip from the mold; depositing a plurality of external contacts on the one side of the leadframe strip, on the contact pads, such that the external contacts protrude from the molding compound; and singulating to provide the integrated circuit package.

Abstract: In one aspect, the present invention relates to a method of manufacturing an integrated circuit package, the method including installing a carrier onto a substrate, attaching a semiconductor die to the substrate, and aligning an assembly over the semiconductor die, wherein the assembly includes a heat sink and a thermally conductive element. This aspect further includes resting the assembly on the carrier such that the thermally conductive element does not directly contact the semiconductor die, and encapsulating the thermally conductive element and the heat sink such that a portion of the heat sink is exposed to the surroundings of the package.

Abstract: The present invention relates to an integrated circuit package and method of manufacturing an integrated circuit package. In one aspect, the present invention relates to an integrated circuit package including a lead frame having a lead with an inner pad and an outer pad connected by a connection member, wherein a region of the inner pad and a region of the outer pad are separated by a channel extending through a width of the lead. Such an integrated circuit package further includes a semiconductor die electrically coupled with the inner pad of the lead, and an encapsulant material encapsulating at least a portion of said lead frame, wherein a portion of said outer pad is exposed.

Abstract: In one aspect, the present invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of the substrate, mounting a semiconductor die on the strip, at least a portion of the semiconductor die being disposed inside the cavity, encapsulating in a molding material at least a portion of the first surface of the substrate, and removing the strip from the substrate.

Abstract: In one aspect, the present invention relates to an integrated circuit package includes a scmiconductor die electrically connected to a substrate, a heat sink having a top and a side portion, the heat sink further including an extending finger when viewed from a top of the package, the extending finger including the side portion of the heat sink, a thermally conductive element thermally coupled with an interposed between both the semiconductor die and the heat sink, wherein the thermally conductive element does not directly contact the semiconductor die, and an encapsulant material encapsulating the thermally conductive element and the heat sink such that the top portion and the side portion of the heat sink are exposed to the surroundings of the package.

Abstract: Leadless plastic chip carriers are formed from a matrix of lead frames provided in a section of a metal strip. Each lead frame in the matrix includes a die-attach pad and multiple leads disposed in close proximity to the die-attach pad. After a semiconductor die is attached to each of the die-attach pad and wire-bonded, the leadless plastic chip carriers are formed by providing a plastic encapsulation which exposes the bottom sides of the die-attach pad and the leads. The bottom sides of the leads serve as solder pads to be used for attaching the leadless plastic chip carrier to a printed circuit board.