Patents Assigned to ASAT Limited
  • Publication number: 20110284495
    Abstract: Various structures and fabrication methods for leadless plastic chip carrier (QFN) packages which utilize carriers in strip format, wherein the leads (or terminals) are formed to be electrically isolated from one another within each unit and in which the units are formed to be electrically isolated from one another within the strip using chemical etching techniques.
    Type: Application
    Filed: September 20, 2007
    Publication date: November 24, 2011
    Applicant: ASAT LIMITED
    Inventors: Tung Lok Li, Kwok Cheung Tsang, Kin Pui Kwan
  • Patent number: 7091581
    Abstract: A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bonding the semiconductor die to ones of the contact pads; releasably clamping the leadframe strip in a mold by releasably clamping the contact pads; molding in a molding compound to cover the semiconductor die, the wire bonds and a portion of the contact pads not covered by the clamping; releasing the leadframe strip from the mold; depositing a plurality of external contacts on the one side of the leadframe strip, on the contact pads, such that the external contacts protrude from the molding compound; and singulating to provide the integrated circuit package.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: August 15, 2006
    Assignee: ASAT Limited
    Inventors: Neil McLellan, Geraldine Tsui Yee Lin, Chun Ho Fan, Mohan Kirloskar, Ed A. Varga
  • Patent number: 7015072
    Abstract: In one aspect, the present invention relates to a method of manufacturing an integrated circuit package, the method including installing a carrier onto a substrate, attaching a semiconductor die to the substrate, and aligning an assembly over the semiconductor die, wherein the assembly includes a heat sink and a thermally conductive element. This aspect further includes resting the assembly on the carrier such that the thermally conductive element does not directly contact the semiconductor die, and encapsulating the thermally conductive element and the heat sink such that a portion of the heat sink is exposed to the surroundings of the package.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: March 21, 2006
    Assignee: ASAT Limited
    Inventors: Edward G. Combs, Robert P. Sheppard, Tai Wai Pun, Hau Wang Ng, Chun Ho Fan, Neil Robert McLellen
  • Patent number: 6940154
    Abstract: The present invention relates to an integrated circuit package and method of manufacturing an integrated circuit package. In one aspect, the present invention relates to an integrated circuit package including a lead frame having a lead with an inner pad and an outer pad connected by a connection member, wherein a region of the inner pad and a region of the outer pad are separated by a channel extending through a width of the lead. Such an integrated circuit package further includes a semiconductor die electrically coupled with the inner pad of the lead, and an encapsulant material encapsulating at least a portion of said lead frame, wherein a portion of said outer pad is exposed.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: September 6, 2005
    Assignee: ASAT Limited
    Inventors: Serafin Pedron, Neil Robert McLellan, Lin Tsui Yee
  • Patent number: 6790710
    Abstract: In one aspect, the present invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of the substrate, mounting a semiconductor die on the strip, at least a portion of the semiconductor die being disposed inside the cavity, encapsulating in a molding material at least a portion of the first surface of the substrate, and removing the strip from the substrate.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: September 14, 2004
    Assignee: ASAT Limited
    Inventors: Neil Robert McLellan, Chun Ho Fan, Edward G. Combs, Tsang Kwok Cheung, Chow Lap Keung, Sadak Thamby Labeeb
  • Patent number: 6734552
    Abstract: In one aspect, the present invention relates to an integrated circuit package includes a scmiconductor die electrically connected to a substrate, a heat sink having a top and a side portion, the heat sink further including an extending finger when viewed from a top of the package, the extending finger including the side portion of the heat sink, a thermally conductive element thermally coupled with an interposed between both the semiconductor die and the heat sink, wherein the thermally conductive element does not directly contact the semiconductor die, and an encapsulant material encapsulating the thermally conductive element and the heat sink such that the top portion and the side portion of the heat sink are exposed to the surroundings of the package.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: May 11, 2004
    Assignee: ASAT Limited
    Inventors: Edward G. Combs, Robert P. Sheppard, Tai Wai Pun, Hau Wan Ng, Chun Ho Fan, Neil Robert McLellen
  • Patent number: 6724071
    Abstract: A molded plastic package for semiconductor devices incorporating a heat sink, controlled impedance leads and separate power and ground rings is described. The lead frame of the package, separated by a dielectric layer, is attached to a metal heat sink. It has more than one ring for power and ground connections. The die itself is attached directly onto the heat sink through a window on the dielectric and provides high power dissipation. The package is molded using conventional materials and equipment.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: April 20, 2004
    Assignee: ASAT, Limited
    Inventor: Edward G. Combs
  • Patent number: 6552417
    Abstract: A molded plastic package for semiconductor devices incorporating a heat sink, controlled impedance leads and separate power and ground rings is described. The lead frame of the package, separated by a dielectric layer, is attached to a metal heat sink. It has more than one ring for power and ground connections. The die itself is attached directly onto the heat sink through a window on the dielectric and provides high power dissipation. The package is molded using conventional materials and equipment.
    Type: Grant
    Filed: January 9, 2001
    Date of Patent: April 22, 2003
    Assignee: Asat, Limited
    Inventor: Edward G. Combs
  • Patent number: 6545347
    Abstract: A plastic integrated circuit package includes a lead frame having numerous leads, a die attach pad and a ground ring. In one embodiment, the plastic integrated circuit package is provided as a plastic leadless chip carrier. Slots provided between the die attach pad and the ground ring provides support and prevent delamination from the plastic molding compound and enhanced moisture-resistance, thus resulting in a highly reliable integrated circuit package, even in the face of high temperature cycles, such as solder reflows.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: April 8, 2003
    Assignee: ASAT, Limited
    Inventor: Neil McClellan
  • Patent number: 6326678
    Abstract: A molded plastic package for semiconductor devices incorporating a heat sink, controlled impedance leads and separate power and ground rings is described. The lead frame of the package, separated by a dielectric layer, is attached to a metal heat sink. It has more than one ring for power and ground connections. The die itself is attached directly onto the heat sink through a window on the dielectric and provides high power dissipation. The package is molded using conventional materials and equipment.
    Type: Grant
    Filed: September 3, 1993
    Date of Patent: December 4, 2001
    Assignee: Asat, Limited
    Inventors: Marcos Karnezos, S. C. Chang, Edward G. Combs, John R. Fahey
  • Patent number: 6285075
    Abstract: An integrated circuit package includes a ceramic ring having an inside cavity for accommodating a semiconductor die. Conductive traces are provided on the ceramic ring so as to serve as power and ground signal busses. Power and ground connection pads on the semiconductor die can be commonly bonded to these conductive traces, which are in turn commonly bonded to selected pins of the lead frame. In addition, an acrylic adhesive is used as a moisture-resistant adhesive.
    Type: Grant
    Filed: November 2, 1998
    Date of Patent: September 4, 2001
    Assignee: ASAT, Limited
    Inventors: Edward G. Combs, Robert Sheppard
  • Patent number: 6284569
    Abstract: A carrier ring provides a stiffening function for assembling flexible circuits or semi-rigid circuits. The carrier ring is attached to a substrate adapted for attachment of a matrix of semiconductor dies. The carrier ring is provided with mold gates and mold vents for use with a transfer molding step to provide encapsulation for the semiconductor dies. Alignment and indexing marks on the carrier ring allows use of conventional assembly process flows in conventional assembly equipment. The height of the carrier ring also provides a means of providing integrated circuits with a predetermined thickness.
    Type: Grant
    Filed: May 10, 1999
    Date of Patent: September 4, 2001
    Assignee: ASAT, Limited
    Inventors: Robert P. Sheppard, Edward G. Combs
  • Patent number: 6242281
    Abstract: Leadless plastic chip carriers are formed from a matrix of lead frames provided in a section of a metal strip. Each lead frame in the matrix includes a die-attach pad and multiple leads disposed in close proximity to the die-attach pad. After a semiconductor die is attached to each of the die-attach pad and wire-bonded, the leadless plastic chip carriers are formed by providing a plastic encapsulation which exposes the bottom sides of the die-attach pad and the leads. The bottom sides of the leads serve as solder pads to be used for attaching the leadless plastic chip carrier to a printed circuit board.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: June 5, 2001
    Assignee: ASAT, Limited
    Inventors: Neil Mclellan, Nelson Fan
  • Patent number: 6229200
    Abstract: Leadless plastic chip carriers are formed from a matrix of lead frames provided in a section of a metal strip. Each lead frame in the matrix includes a die-attach pad and multiple leads disposed in close proximity to the die-attach pad. After a semiconductor die is attached to each of the die-attach pad and wire-bonded, the leadless plastic chip carriers are formed by providing a plastic encapsulation which exposes the bottom sides of the die-attach pad and the leads. The bottom sides of the leads serve as solder pads to be used for attaching the leadless plastic chip carrier to a printed circuit board.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: May 8, 2001
    Assignee: ASAT Limited
    Inventors: Neil Mclellan, Nelson Fan
  • Patent number: 6111324
    Abstract: A carrier ring provides a stiffening function for assembling flexible circuits or semi-rigid circuits. The carrier ring is attached to a substrate adapted for attachment of a matrix of semiconductor dies. The carrier ring is provided with mold gates and mold vents for use with a transfer molding step to provide encapsulation for the semiconductor dies. Alignment and indexing marks on the carrier ring allows use of conventional assembly process flows in conventional assembly equipment. The height of the carrier ring also provides a means of providing integrated circuits with a predetermined thickness.
    Type: Grant
    Filed: February 5, 1998
    Date of Patent: August 29, 2000
    Assignee: ASAT, Limited
    Inventors: Robert P. Sheppard, Edward G. Combs
  • Patent number: 5843808
    Abstract: A TAB Grid Array (TGA) package allows automated assembly using established manufacturing equipment similar to those used in the production of plastic ball grid Array (PBGA) package assembly. The TGA package are formed, using as starting material, a metal strip having the same critical dimensions and tooling holes as those used for a PBGA package. In this invention, the stiffener is designed to serve as a carrier throughout the assembly of the TGA package. The wire bonded TGA cavity package, including the solder balls, is first fully assembled prior to the attachment of the semiconductor die. Subsequently, the semiconductor die is attached to the stiffener, wires are bonded between the semiconductor die and the tape frame, and the entire assembly is encapsulated. The process of the present invention provides a high device assembly yield usually not achievable by the PBGA packages.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: December 1, 1998
    Assignee: ASAT, Limited
    Inventor: Marcos Karnezos
  • Patent number: 5596231
    Abstract: A structure and a method provide an assembly for receiving an integrated circuit die. The assembly comprises a heat sink selectively coated with electrically insulative material. The heat sink is attached by one of various methods directly on to the integrated circuit die and a lead frame for external electrical connections. The heat sink is formed as a stepped structure to increase the path of moisture penetration so as to improve moisture resistance and reliability. In one embodiment of the present invention, the electrically insulative material comprises anodized aluminum, which is formed on the heat sink by a vapor deposition step, followed by a hard anodization step. Other electrical insulative material which can be thinly applied on the surface of the heat sink are non-conductive resins and polymers. The heat sink is formed out of copper or a copper alloy, selected for strength and electrical and thermal conductivities.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: January 21, 1997
    Assignee: Asat, Limited
    Inventor: Edward G. Combs