Abstract: A joystick for a computer game which comprises a stick lever, a trigger button and a function button. In the joystick, when the function button is pressed down while the stick lever is inclined in one of directions or the trigger button is depressed, an operation specified by the inclination direction of the stick lever or by the trigger button can be executed intermittently or continuously, so that, even if the trigger button is operated long, it is possible to enhance the operation of the joystick, to reduce the fatigue of a player and to extend the life of the joystick.

Abstract: A video display control system displays a multicolor animation pattern on a screen of a video display unit. The video display control system is mainly constructed by a video RAM (VRAM) and a video display processor (VDP). The VRAM stores animation pattern data, display position data and at least two color data. The VDP reads these data and makes an animation pattern image displayed in at least two colors at a display position on the screen. The animation pattern image, two colors and display position are determined by the animation pattern data, two color data and display position data. In another video display control system, the VRAM stores at least two sets of animation pattern data, display position data and color data. When displaying two animation patterns, the VDP effects a logical operation on the two color data with respect to the overlapping portion of the two patterns and makes the overlapping portion displayed in a new color corresponding to the operation result.

Abstract: An image display apparatus reads color data and attribute data accompanied with the color data from a RAM of a look-up table (LUT) in accordance with each color code read from a video memory (VRAM). The read color data is subjected to a data modification determined by the read attribute data, and a color of each display dot is determined in accordance with the color data obtained as the result of the data modification. According to this image display apparatus, an image and the color thereof can be displayed without storing all the color codes of the image into the VRAM, so that the load on the CPU can be reduced and the image can be displayed at a high speed. The LUT can be omitted by storing, correspondingly to each display dot, display data composed of color data and attribute data in the VRAM. The circuit for effecting the data modification may comprise a plurality of registers and an operation circuit for effecting an operation on data contained in the registers.

Abstract: A display controller can display a cursor having sufficient contour irrespective of the background color. The display controller has two cursor pattern memories from which first and second cursor patterns are read in such a timing that the first cursor pattern is displayed at a selected position on the screen and that the second cursor pattern is superimposed on the first cursor pattern. The display controller also has two registers storing therein first and second color codes corresponding respectively to the first and second cursor patterns. The color of the first cursor pattern is determined by a color code obtained by subjecting the first color code and a background color code read from a video memory to a logical multiplication, and the color of the second cursor pattern is determined by a color code obtained by subjecting the color code of the first cursor pattern and the second color code to an exclusive-OR operation.

Abstract: A display control system has a digital interface therein. When software using a color display is executed and displayed in a monochrome monitor, this system is responsive to color code information to arbitrarily select either a hatching pattern conversion or a grey scale display according to application software or the like. The system can thus discriminate the display contents thereof.In a color monitor that permits input of a plurality of digital signals, the display control system can convert a given piece of color code information into digital video signals according to frames and display positions in a given area of a display screen for display of natural colors.

Abstract: A video display processor (VDP) is connectable to an input control device such as a light pen and a mouse. The VDP comprises a counter circuit which is composed of an X counter and a Y counter. When a mouse mode is selected, X and Y pulse signals are supplied to the X and Y counters so that the contents of the X and Y counters represent the amount of movement of the mouse. When a central processing unit (CPU) connected to the VDP reads the contents of the X and Y counters in this mouse mode, the X and Y counters are reset. When a light pen mode is selected, the X and Y counters effect a count operation of a clock signal generated in the VDP in synchronism with the display of image on a screen so that the contents of the X and Y counters represents X-Y coordinates of a display element which is currently displayed on the screen.

Abstract: A color video display apparatus displays a first image represented by luminance and color difference data stored in a VRAM and a second image represented by color codes stored in the same VRAM on a screen of a CRT display unit in a superimposed relation. Each address of the VRAM stores the luminance data and an attribute bit of the corresponding display dot of the first image, and the color difference data is formed with respect to each group of a predetermined number of display dots of the first image and stored in a predetermined number of addresses of the VRAM. The color code of each dot of the second image is stored in the corresponding addresses of the VRAM. The data sequentially read from the addresses of the VRAM are shifted into a register group composed of a predetermined number of registers.

Abstract: A display control system can implement a gray-scale display of an image composed of a plurality of display dots on a display screen. A plurality of luminance data each representing an intensity level of a corresponding one of the plurality of display dots are first generated. Each luminance data is then converted into a pulse signal whose pulse number corresponds to an intensity level of the corresponding display dot represented by the luminance data. And, each display dot on the display screen is activated in accordance with a corresponding one of the thus produced pulse signals. To eliminate flicker of the display dots, the display dots on the display screen are grouped into a plurality of display sections each composed of a predetermined number of adjacent display dots, and if the display dots in one display section are equal in intensity level, these display dots are activated by the pulse signals which are equal in pulse-number but different in phase.

Abstract: A display controller displays an image on either of a CRT display unit and a liquid crystal display unit (LCD) having upper and lower screens in accordance with image data stored in a memory. When a CRT display unit is driven, an address generating circuit calculates at the beginning of each horizontal scanning an address of the memory corresponding to the leftmost display position on the current horizontal scanning line in accordance with the vertical position of the horizontal scanning line and the number of display positions on a horizontal scanning line, and stores data representing the address in a first register. The data in the first register is incremented in accordance with the horizontal scanning and fed to the memory to read the image data.

Abstract: A display controller which can display a cursor on either of a CRT display or a liquid crystal type display device is described. The liquid crystal type display device is a type that has an upper and lower display blocks which are scanned substantially in parallel. This display controller allows the display position of the cursor to be designated in the same manner, independent of the type of display device used. The display controller operates in a time sharing manner, alternately on the upper and lower display blocks of the liquid crystal device. Two groups of data corresponding to these upper and lower blocks are formed and are supplied to the liquid crystal display device substantially in parallel. X and Y coordinate positions of the cursor position are also stored. The cursor pattern signal for the liquid crystal display device is also stored in a time shared manner.

Abstract: An improved display control system for use in a computer is disclosed which is equipped with functions of X, Y addressing and area movement so as to reduce the execution time necessary for display operations of the computer. Also, in this display control system, means for executing line commands is composed of the hardware so as to reduce the execution time necessary for display operations on the line commands.

Abstract: A video display processor (VDP) produces a video signal by which a black and white image of an increased gradation can be displayed on a video display unit. The VDP reads from a video RAM (VRAM) either color codes each representative of a color of each display element, or amplitude data representative of amplitudes of a video signal to be reproduced. When displaying an image based on the color codes, the color codes are converted by a color palette circuit into color data each composed of three primary color data, and then supplied to a digital color encoder. The digital color encoder multiplies each of the three color data by predetermined coefficients at proper phase timings to output data representative of three chrominance signals. This output data is summed by an adder circuit and then converted into an analog signal to be supplied to the video display unit as the video signal. When displaying an image based on the amplitude data, the color palette circuit converts the amplitude data into gradation data.

Abstract: There is provided a video display controller which can vertically and horizontally shift a whole video image displayed on a screen of a video display unit. The video display controller comprises an image data read circuit which reads the image data from a video RAM, a register into which data representative of amount of shift of the video image is stored by a central processing unit, and a first counter which cyclicly counts a clock signal. An adder adds the data contained in the register and a count output of the first counter, and at a timing determined by this addition result a predetermined value is preset into a second counter. This second counter counts the clock signal from the predetermined value, and the image data read by the image data read circuit is outputted to the video display unit at a timing in accordance with a count output of this second counter. The register, first counter, adder and second counter are provided in each of vertical and horizontal scanning control circuits.

Abstract: An inexpensive A-D converter circuit comprising a signal conversion circuit for converting an analog signal into a digital signal based on a reference voltage, in which the whole reference voltage is varied periodically, the output signal just ahead of the signal conversion circuit is held by an output buffer, and the output signal of the signal conversion circuit and the signal just ahead are added. Also, in the A-D converter circuit, after the above addition, a difference between two consecutive pieces of data of the output data of the signal conversion circuit is detected. When the data difference is within a given range, then the output of the above addition is selected, while for the data difference exceeding the given range double the above output is selected.

Abstract: A video display control system for displaying a video image on a screen of a video display unit. This video display control system basically comprises a VRAM (video RAM) and a video display processor (VDP). The VRAM has memory locations corresponding to display elements on the screen. The VDP includes a first register for receiving area information identifying a display area on the screen, an address generator for generating addresses of memory locations corresponding to the display area in accordance with the area information, and a memory accessing circuit for accessing the memory locations having the addresses. Therefore, the memory accessing operation through this VDP does not need a complicated support by a central processing unit. The VDP further comprises a second register for storing a color code supplied from an external device or read from the VRAM.

Abstract: A video display controller is provided with a color palette circuit which is capable of converting, at a high conversion rate, color codes read from a VRAM (video RAM) into RGB color data to be supplied to a CRT display unit. The color palette circuit comprises a plurality of color data registers each storing one RGB color data and is supplied with a timing signal synchronized with the display timing of display elements on the CRT display screen. Each color code data including at least two color codes and read from an address of the VRAM is first supplied to a selection circuit which includes at least two decoders. Each decoder decodes the corresponding color codes to generate a selection signal which enables one of the color data registers to output the RGB color data contained therein.

Abstract: A video display processor (VDP) for use with a central processing unit, a video RAM (VRAM) and a video display unit is capable of writing video image data supplied from an external video device such as a television set into the VRAM. The VDP comprises a first input terminal for receiving the external video image data and a second input terminal for receiving horizontal and vertical synchronization signals from the external video device. The VDP generates address data in accordance with the horizontal and vertical synchronization signals and supplies the address data to the VRAM when processing of the external video image data is designated. The VDP also supplies the received external video image data to the VRAM thereby to write the external video image data into addresses of the VRAM designated by the address data.

Abstract: A video display controller which can display foregrounds as well as backgrounds of display patterns on a screen of a video display unit in a plurality of colors. The video display controller comprises a plurality of color information registers, in each of which a pair of color code data representative of foreground and background colors of one display pattern are stored. A memory is provided for storing a plurality of pattern data, a plurality of pattern name data each designating one of the display patterns to be displayed on a respective one of display portions of the screen, and a plurality of color selection data each corresponding to a respective one of the display portions. A sequence controller sequentially reads the pattern data designated by the pattern name data and the color selection data in accordance with synchronization signals.

Abstract: A video display control system comprises a video display processor (VDP) which is capable of accessing to a video RAM (VRAM) at an extremely high-speed. The VRAM used in this system comprises first and second dynamic RAMs each having an address input terminal to which row address data and column address data are supplied, a row address strobe input terminal, a column address strobe input terminal, and a data input/output terminal. The row address data is latched at the leading edge of a row address strobe signal applied to the row address strobe input terminal, while the column address data is latched at the leading edge of a column address strobe signal applied to the column address strobe input terminal. An access to an address of each dynamic RAM is established when both of the row and column address data are latched. The VDP comprises a VRAM interface for controlling an access to the first and second dynamic RAMs which is connected to the RAMs through a common address bus.