Abstract: A signal used in the transmission of data in a communication system (for example in an ATM network), comprised of immediately successive cells. For the purpose of cell synchronization, filler cells (I) containing a predefined bit pattern are provided. This pattern is provided with an error protection code that differs from the error protection code used for the user data. Even if the user data should coincidentally contain the predefined bit pattern, the synchronization circuit will not be able to be simulated, since this false bit pattern is provided with a different error protection code. In order to test and ensure the synchronization state, a BIP value at the end of the cell is checked at the receiver end.

Abstract: A signal used in the transmission of data in a communication system (for example in an ATM network), comprised of immediately successive cells. For the purpose of cell synchronization, filler cells (I) containing a predefined bit pattern are provided. This pattern is provided with an error protection code that differs from the error protection code used for the user data. Even if the user data should coincidentally contain the predefined bit pattern, the synchronization circuit will not be able to be simulated, since this false bit pattern is provided with a different error protection code. In order to test and ensure the synchronization state, a BIP value at the end of the cell is checked at the receiver end.

Abstract: A signal used in the transmission of data in a communication system including immediately successive cells for the purpose of cell synchronization, includes filler cells containing a predefined bit pattern. This pattern is provided with an error protection code that differs from an error protection code used for user data. Even if the user data should coincidentally contain the predefined bit pattern, the synchronization circuit will not be able to be simulated, since this false bit pattern is provided with a different error protection code. In order to test and ensure the synchronization state, a BIP (bit interleaved parity) value at the end of the cell is checked at the receiver end.

Abstract: Several nodes are connected to a ring structure by means of communication lines in a network for packet-oriented data traffic. Each node is connected to lines of the ring structure. A buffer circuit is provided between the high speed interfaces for reading a routing information on the head of a data packet. The buffer circuits are structured in such a manner that the delay time in the transit traffic is smaller than, for example, 10 .mu.s. Several users are connected at the node. A wait line circuit is provided for each user. A controller ensures the processing of the data packets in the transit, insert and extract modes.

Abstract: Four parallel lines are provided for the guided transmission of a data flow with a high rate (sub-GHz range). Two data bits per transmission clock are transmitted via these lines. The other two remaining lines are used for signaling certain changes in both data bits. Data transmission and signaling are accomplished on the basis of the Grey code. In other words, only one of the four lines changes state per clock. The interface according to the invention has reduced sensitivity to signal skew and permits simple clock recovery in terms of circuit engineering.

Abstract: For controlling the data traffic in an ATM network, in which a number of nodes are connected via a closed loop, and in which each node may be equipped with a number of access ports for sending and receiving ATM cells, the ATM cells are processed separately in each node based upon their assignment to a QoS (quality of service) class in a predefined QoS classification. In each access port, each QoS class is assigned a separate queue. The data traffic in the closed loop is monitored separately, based upon QoS class, by a cell monitor. If a performance characteristic of a QoS class is not fulfilled in the closed loop, then at least one back-pressure signal will be generated, which will serve to suppress at least one assigned queue of the access port. The monitoring of the data traffic can be implemented via a leaky-bucket system.

Abstract: In a process for demodulation of a received signal that contains, in addition to data to be transmitted, a preset synchronization sequence, the following is done to estimate a frequency shift. At least two nonoverlapping partial sequences of the synchronization sequence are picked off. Using a least-square process, the coefficients of the channel step response at each observation window are determined. The frequency shift, in the form of a phase rotation per symbol, is then estimated.

Abstract: A flat three-dimensional antenna is built in three planes. In the first plane is a base plate, in the second plane is a slot divider bent in a U-shape, and in the third plane is resonant structure above the slot divider. The slot divider has a middle part with a length of preferably .lambda./4 and two limbs of .lambda./8 of the same length. With the base plate the slot divider forms a .lambda./2 antenna slot, while the resonant structure with the slot divider defines a shorter second antenna slot. The antenna is characterized by a large bandwidth and omnidirectional radiation characteristic. Perpendicular to the base plate there is essentially no radiation. Feeding takes place preferably via a stripline which is routed between two limbs to a middle part. Impedance matching of the antenna is achieved by suitable dimensioning of the stripline. The antenna can be built equally well in air as well as in a dielectric such as a ceramic block.

Abstract: A method and apparatus for receiving a signal by the ETS/HIPERLAN standard. In the method decoding is done by the BCH standard. Differential pre-coding is done and integration for cancelling transmitter side differential pre-coding is done only after BCH encoding. The apparatus contains a non-coherent demodulation a BCH decoder and an integrator.

Abstract: In a process for the coherent demodulation of a reception signal, several coefficients of the channel impulse response are determined beforehand. The coefficients are divided into at least two gain taps and at least one loss tap. The loss taps are utilized for a feedback filter to eliminate a corresponding signal component. The signal cleared up in this manner is estimated in a log-likelihood equalizer on the basis of gain taps. The process is characterized in that neither filter training nor high mathematical effort are required for determining the equalizer coefficients. There is also no error floor for the high frequency band signal. The quantity of operations required per symbol in the detection phase is comparatively small.

Abstract: A wireless communication system for asynchronous transfer mode includes the dynamic assignment of signalling virtual channels and/or virtual paths for communications between a mobile terminal and a controller or control function. An access point associated with the wireless mobile terminal is transparent for transmitted data and control information. The dynamic assignment of the signalling virtual channel (SVC) takes place in the event of new registration to the system and handover from one access point to another. The protocol uses finite state machines and timers at the mobile terminal and at the control function. For new registrations, an assignment channel is used on a broadcast uplink from the mobile terminal to the control function to request the SVC, while the response from the control function is transmitted on the downlink broadcast channel. The response contains the unique SVCI to be used by the mobile terminal and the control function for further signalling between them.

Abstract: In digital data packets comprising a first datum from which a second datum can be unequivocally computed, e.g. an error correction value, one or a plurality of additional data can be introduced by manipulating said second datum without altering the structure of the data packet. For this purpose, one or a plurality of bits of the second datum are modified in an unequivocally reversible manner, e.g. inverted, according to the additional datum which is also digital. The recuperation of the additional data is effected by comparing comparative values which are obtained by reversing all possible combinations of additional data in a received data packet to a value which is computed from the first datum of the data packet: The presence of the corresponding combination of additional data results from the consistency of the latter with one of said comparative values. Another possibility is to limit the inquiry to a fraction of the possible combination.

Abstract: In an ATM switch, the total required buffer storage is concentrated in a central memory which is used by all input and output channels. The connection between the input and output channels and the memory is established by a synchronous bus. The time allocation on the bus is designed in such a manner that within the transmitting time of a data cell according to the ATM norm, e.g., over a wide band network, a time slice which is sufficient for the transfer of a complete data cell between an input or an output and the memory is allocated to each input and output. The memory is fixedly divided into areas of the same size, each of the areas serving as a buffer for a respective input. Due to the simple time allocation of the bus it is possible to combine a plurality of input and output channels in an input/output unit and to still realize the latter in a small number of integrated circuits. For the memory, unexpensive standard memory devices can be used.

Abstract: A wireless communication system for asynchronous transfer mode includes the dynamic mapping of ATM cells on a wireless ATM link into a unique Virtual Path on a wired ATM link, and in the reverse direction as well. The access point includes a radio medium access controller which assigns a unique radio connection identifier RCI to the wireless link established between the access point and a mobile terminal. The Virtual Path identifier (VPI) used on the fixed link is selected based on the RCI assigned by the access point. The radio connection identifier RCI remains unchanged as long as the mobile terminal is associated with that access point. ATM cells sent from the control function include the VPI and are mapped by the access point into the connection referenced by the RCI. ATM cells from the mobile terminal are received on a particular connection. According to the connection identifier (RCI) cells are mapped by the access point into a particular Virtual Path, which corresponds to the RCI.

Abstract: A NT2 (Network Termination type 2) unit comprises a terminal and control unit and an arbitrary number of identical switching units (39) which are interconnected in a loop configuration by means of two connecting lines (123, 124). Similar to an NT1 (Network Termination type 1) unit, each of the switching units (39) comprises two mutually opposed transmitting paths (23, 24) for ATM (Asynchronous Transfer Mode) cells as well as two input/output circuits (22.1, 22.2) to which the connecting lines (123, 124) are connected. The switching unit (39) further comprises a third input/output circuit (22.3) allowing the connection of terminal equipment. Finally, the switch unit (39) is provided with an extractor (31) and an inserter (32) which are inserted in the transmitting paths (23, 24) and are connected to the third input/output circuit (22.3) via connecting lines (35.1, 35.2).

Abstract: The reflection modulator (11), serving the purpose of modulating a light beam emerging from an optical fiber (42) and re-entering the same, is essentially based on a microstructural Fabry and Perot interferometer. The interferometer is formed by two parallel reflecting layers (18, 20) which are electrically conductive, electrically insulated from each other, and connected to electric terminals (28, 30), and an air gap (19) which is comprised between them. A mechanical excursion of one (20) of the two reflecting layers can thus be produced by an electric wanted signal (NS). The reflecting layers (18, 20) are disposed on a base block (14) of monocrystalline silicon having two parallel main surfaces (15, 16) each of which is covered by two passivating coatings (25, 35, 26, 36). The base block (14) is provided with a recess on one (16) of the main surfaces. An optical fiber (42) is fastened in said recess by means of an adhesive (44) in such a manner that the fiber end is completely enclosed by said adhesive.

Abstract: A process for transmitting digital signals, in which the digital data are coded differentially in symbols of a symbol period T.sub.s (2.1, 2.2), the symbols transmitted with the Q component being delayed by T.sub.s /2, relative to those of the I component, to achieve a time-staggering. A cross interference of the I and Q components, occurring on the receiver end and caused by the differential coding nd the time staggering, is resolved with a trellis decoder (10), for example. As a result, a differential offset QPSK process achieved on this basis combines the advantages of DQPSK and OQPSK procedures.

Abstract: All the information sections of a processed data structure, including pre-header, tail and extra section, header and payload, can be selectively copied in a node of a communication network by means of a copy mask (12) associated with a copy block (11). A combination of an insert block (14) and an insert mask (15) is used for selectively writing to all the information sections in the data structure. In order to increase the capacity of the data structure, the length of the pre-header or tail can be increased. In the path between an input interface (10) and the insert block (14) there is an adjustable delay block (13) into which the data structure can be copied as a whole. A microprocessor (25) is coupled to all the processing units (10)-(17) and (22)-(24) of the system and serves for presetting the two masks for selecting the information to be copied and inserted.

Abstract: An apparatus and method for controlling the common memory of an ATM-node. The nodes serve for the continuous reception and onward routing of address-labelled cells with uniform length and uniform construction. The apparatus includes means for management and control and a sequencer for managing the storage blocks of the common memory and for controlling the sequential reading in and reading out of cells, respectively, into or out of said storage blocks. The circuits for management and control include at least one addressable read/write store, a monitor logic, an input logic, a bus- and control-logic, and a comparator, the read/write store includes a number of storage locations equal to the third plurality plus two times the second plurality multiplied by the quantity, plus 2. Every storage location of the read/write store is constructed for storing an address.

Abstract: A synchronizing circuit comprises a controllable timer (9) and a PN-code generator (10) controllable thereby with at least three outputs (11.1, 11.2, 11.3), for the production of at least three PN-code signals phase-shifted with respect to one another. The PN-code signals phase-shifted with respect to one another are correlated, in parallel correlation paths, with the received signal. Upon the presence of a time drift, the phase position of the trailing PN-code signal, for example, is changed so that this signal is now leading. Thereby, the control range is shifted. At the same time, reassignment is effected between the correlation path and the demodulating output in such a way that in all cases the correlation path that is in the middle with respect to time and that has the maximum correlation power is utilized for demodulation.