Abstract: In digital data packets comprising a first datum from which a second datum can be unequivocally computed, e.g. an error correction value, one or a plurality of additional data can be introduced by manipulating said second datum without altering the structure of the data packet. For this purpose, one or a plurality of bits of the second datum are modified in an unequivocally reversible manner, e.g. inverted, according to the additional datum which is also digital. The recuperation of the additional data is effected by comparing comparative values which are obtained by reversing all possible combinations of additional data in a received data packet to a value which is computed from the first datum of the data packet: The presence of the corresponding combination of additional data results from the consistency of the latter with one of said comparative values. Another possibility is to limit the inquiry to a fraction of the possible combination.

Abstract: In an ATM switch, the total required buffer storage is concentrated in a central memory which is used by all input and output channels. The connection between the input and output channels and the memory is established by a synchronous bus. The time allocation on the bus is designed in such a manner that within the transmitting time of a data cell according to the ATM norm, e.g., over a wide band network, a time slice which is sufficient for the transfer of a complete data cell between an input or an output and the memory is allocated to each input and output. The memory is fixedly divided into areas of the same size, each of the areas serving as a buffer for a respective input. Due to the simple time allocation of the bus it is possible to combine a plurality of input and output channels in an input/output unit and to still realize the latter in a small number of integrated circuits. For the memory, unexpensive standard memory devices can be used.