Patents Assigned to ASE Electronics Inc.
  • Patent number: 8059422
    Abstract: A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: November 15, 2011
    Assignees: Advanced Semiconductor Engineering, Inc., ASE Electronics Inc.
    Inventors: Ho-Ming Tong, Shin-Hua Chao, Ming-Chiang Lee, Tai-Yuan Huang, Chao-Yuan Liu, Yung-Cheng Huang, Teck-Chong Lee, Jen-Chieh Kao, Jau-Shoung Chen
  • Publication number: 20090258320
    Abstract: A method of forming measuring targets for measuring the dimensions of a substrate during a substrate manufacturing process is provided. First, a board having a base layer and a conductive layer is provided, wherein the conductive layer is disposed on a surface of the base layer. Then, at least one through hole is formed in the board as a measuring target for measuring the dimensions of the substrate. Next, a plated via is formed in the through hole as another measuring target for measuring the dimensions of the substrate. Thereafter, a patterned dielectric layer is formed on the board to expose the plated via as a next measuring target for measuring the dimensions of the substrate. In the present invention, measuring targets are formed during a substrate manufacturing process and the dimensions of the substrate are measured instantly. The accuracy in process alignment is improved without increasing the fabrication cost.
    Type: Application
    Filed: June 10, 2008
    Publication date: October 15, 2009
    Applicant: ASE Electronics Inc.
    Inventor: Hsiang-Ming Feng
  • Publication number: 20090075027
    Abstract: A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.
    Type: Application
    Filed: July 31, 2008
    Publication date: March 19, 2009
    Applicants: ADVANCED SEMICONDUCTOR ENGINEERING, INC., ASE ELECTRONICS INC.
    Inventors: Ho-Ming Tong, Shin-Hua Chao, Ming-Chiang Lee, Tai-Yuan Huang, Chao-Yuan Liu, Yung-Cheng Huang, Teck-Chong Lee, Jen-Chieh Kao, Jau-Shoung Chen