Patents Assigned to ASE Electronics (M) Sdn. Bhd.
  • Patent number: 9722098
    Abstract: A method of manufacturing a semiconductor device package includes disposing at least one die over a substrate, dispensing a liquid material on the die, and curing the liquid material so that the liquid material forms a protective layer attached to a portion of the die. The method further includes forming an encapsulant covering at least a portion of the substrate and a portion of the die, where the protective layer is exposed from the encapsulant in a cavity defined by the encapsulant. The method further includes removing the protective layer from the die, and disposing a cap over the cavity.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: August 1, 2017
    Assignee: ASE ELECTRONICS (M) SDN BHD
    Inventors: Kam Cheong Chung, Ahmad Zulmuhtasyim, Liang Peng Cheng, Lai Theng Chan
  • Patent number: 6940182
    Abstract: A dam or barrier around the periphery of a die in a flip-chip package changes the shape of the underfill to reduce stress resulting from edge effects. The dam can include a treated region of a substrate having an affinity to an underfill material. The treated region causes liquid underfill material to bead, thereby controlling the wetting angle of the underfill material and shaping the underfill to eliminate sources of stress such as underfill fillet regions that are subject to significant shrinkage. The dammed underfill additionally avoids or reduces the extent of areas having thermal coefficients of expansion that differ from the optimal level because of low filler particle concentration.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: September 6, 2005
    Assignees: Celerity Research Pte. Ltd., ASE Electronics (M) Sdn. Bhd.
    Inventors: Robert M. Hilton, Sabran B. Samsuri
  • Patent number: 6773828
    Abstract: An electroplating process reduces the whisker formation rate that results from an interruption of the electroplating process for an alloy. The process forms a tin strike or a thin layer of a pure(>99.9%) metal on the alloy during an activation operation, so that an interruption in the electroplating process during which the lead frame or other work piece remains in an activation solution etches the pure metal layer rather than the alloy and thus does not unacceptably roughen the surface of the work piece. An exemplary embodiment forms a tin strike on a predominantly copper lead frame during an activation operation and forms an Sn—Pb solder layer on the tin strike during a plating operation. The solder layer is generally more than five times as thick as the tin strike layer.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: August 10, 2004
    Assignee: ASE Electronics (M) Sdn. Bhd.
    Inventors: Heng Ee Ooi, Salmi Abdul Rahman, Chin Yee Fong, Siew Leong Chaw
  • Patent number: 6762509
    Abstract: A flip-chip packaging method for a semiconductor device treats a portion of an interconnect substrate so that a fill material when liquid beads on the treated portion of the interconnect substrate. When the fill material is dispensed on the interconnect substrate to fill a gap under the semiconductor device, the beading of the fill material prevents formation of fillets that might otherwise create a variation in the thermal coefficient of expansion of fill material and/or warp the interconnect substrate. The treated portion of the interconnect substrate can be roughened or coated with a material that differs from other portions of the interconnect substrate and thereby causes beading.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: July 13, 2004
    Assignees: Celerity Research Pte. Ltd., ASE Electronics (M) Sdn. Bhd.
    Inventors: Robert M. Hilton, Sabran B. Samsuri
  • Patent number: 6737752
    Abstract: A flip-chip package uses a substrate having bond pad spacing that matches terminal spacing on a chip at an elevated temperature that is an expected operating temperature of the chip. The elevated temperature can be the midpoint of the desired temperature cycle of the chip so that deformations of the electrical connections in one direction balance deformations in the opposite direction during temperature cycling. Matching spacing at an elevated temperature, even a temperature less than the bonding temperature, permits a better alignment at the bonding temperature for formation of stronger bonds.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: May 18, 2004
    Assignees: Celerity Research Pte. Ltd., ASE Electronics (M) Sdn. Bhd.
    Inventor: Robert M. Hilton
  • Patent number: 6699732
    Abstract: A flip-chip package and packaging method use a substrate having bond pad spacing that matches terminal spacing on a chip at an elevated temperature, such as the temperature of the chip during bonding to the substrate, the melting point of solder used on the chip, a temperature within the range of thermal cycling of the chip, or an operating temperature of the chip. Matching spacing at an elevated temperature permits a better alignment at the bonding temperature for formation of stronger bonds.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: March 2, 2004
    Assignees: Celerity Research Pte. Ltd., ASE Electronics (M) Sdn. Bhd.
    Inventor: Robert M. Hilton
  • Patent number: 6576073
    Abstract: A process for fabricating a BGA flip chip package containing a stiffener or heat spreader monitors edges of the adhesive that attaches the stiffener or heat spreader. The monitoring ensures that the adhesive extends beyond the centers of the outermost solder balls in the BGA. Stress at the edge of the adhesive thus does not cause warping or variations within the BGA.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: June 10, 2003
    Assignees: Celerity Research Pte. Ltd., ASE Electronics (M) Sdn. Bhd.
    Inventors: Robert M Hilton, Sabran Bin Samsuri