Patents Assigned to ASELSAN ELEKTRONIK SANAYI VE TICARET A.S.
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Patent number: 11289704Abstract: Methods of forming a battery include forming a thin graphene cathode on a substrate. A lithium anode is formed and an electrolyte is formed between the thin graphene cathode and the lithium anode.Type: GrantFiled: November 15, 2019Date of Patent: March 29, 2022Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ASELSAN ELEKTRONIK SANAYI VE TICARET A.S.Inventors: Esin Akca, Cagla Akgun, Gokhan Demirci, Damon B. Farmer, Shu-Jen Han, Hareem T. Maune, Dahyun Oh
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Patent number: 10566623Abstract: Batteries and methods of forming the same include a lithium anode, an electrolyte having a high solubility for lithium ions and oxygen, and a thin graphene cathode formed on a substrate. Lithium ions migrate from the lithium anode through the electrolyte to form Li2O2 at a surface of the thin graphene cathode.Type: GrantFiled: June 22, 2017Date of Patent: February 18, 2020Assignees: ASELSAN ELEKTRONIK SANAYI VE TICARET A.S, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Esin Akca, Cagla Akgun, Gokhan Demirci, Damon B. Farmer, Shu-Jen Han, Hareem T. Maune, Dahyun Oh
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Patent number: 10478087Abstract: An open bore coil system enabling electronic steering and rotation of a Field Free Line (FFL) inside a large volume. An FFL is generated by placing two parallel coil pairs (fed with alternating current directions) side by side. Using two of these coil groups, the FFL can be rotated in the plane perpendicular to the coil axes. The FFL can be translated in the rotation plane of the FFL using a coil pair placed on the same axis with the other coils. It can also be translated in the perpendicular plane by asymmetrical coil excitation. As all the coils in the system are parallel, the imaged object can be reached from the sides during imaging.Type: GrantFiled: February 16, 2017Date of Patent: November 19, 2019Assignee: ASELSAN ELEKTRONIK SANAYI VE TICARET A.S.Inventors: Can Baris Top, Huseyin Emre Guven
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Patent number: 10110237Abstract: A detection system and a detection method for detecting the loss of lock between a PLL reference clock signal and a PLL feedback clock signal. The detection system includes a pseudorandom bit sequence generator; a first shift register; a second shift register; a third shift register; a first synchronizer; a second synchronizer; a third synchronizer; a first comparator; a second comparator; and an alarm control unit. The method comprises the steps of, generating an n-bit wide pseudorandom bit sequence; sampling the sequence with PLL reference clock signal, PLL feedback clock signal and inverse of PLL feedback clock signal; re-sampling and re-synchronizing the sampled sequences; comparing re-sampled and re-synchronized sequence, previously sampled with PLL reference clock signal, with re-sampled and re-synchronized sequences, previously sampled PLL feedback clock signal and inverse of PLL feedback clock signal; generating a flag signal if the comparisons give no match.Type: GrantFiled: June 20, 2017Date of Patent: October 23, 2018Assignee: ASELSAN ELEKTRONIK SANAYI VE TICARET A.S.Inventors: Asim Kepkep, Emre Apaydin
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Publication number: 20180231629Abstract: An open bore coil system enabling electronic steering and rotation of a Field Free Line (FFL) inside a large volume. An FFL is generated by placing two parallel coil pairs (fed with alternating current directions) side by side. Using two of these coil groups, the FFL can be rotated in the plane perpendicular to the coil axes. The FFL can be translated in the rotation plane of the FFL using a coil pair placed on the same axis with the other coils. It can also be translated in the perpendicular plane by asymmetrical coil excitation. As all the coils in the system are parallel, the imaged object can be reached from the sides during imaging.Type: ApplicationFiled: February 16, 2017Publication date: August 16, 2018Applicant: ASELSAN ELEKTRONIK SANAYI VE TICARET A.S.Inventors: CAN BARIS TOP, Huseyin Emre Guven
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Publication number: 20180054207Abstract: A detection system and a detection method for detecting the loss of lock between a PLL reference clock signal and a PLL feedback clock signal. The detection system includes a pseudorandom bit sequence generator; a first shift register; a second shift register; a third shift register; a first synchronizer; a second synchronizer; a third synchronizer; a first comparator; a second comparator; and an alarm control unit. The method comprises the steps of, generating an n-bit wide pseudorandom bit sequence; sampling the sequence with PLL reference clock signal, PLL feedback clock signal and inverse of PLL feedback clock signal; re-sampling and re-synchronizing the sampled sequences; comparing re-sampled and re-synchronized sequence, previously sampled with PLL reference clock signal, with re-sampled and re-synchronized sequences, previously sampled PLL feedback clock signal and inverse of PLL feedback clock signal; generating a flag signal if the comparisons give no match.Type: ApplicationFiled: June 20, 2017Publication date: February 22, 2018Applicant: ASELSAN ELEKTRONIK SANAYI VE TICARET A.S.Inventors: Asim KEPKEP, Emre APAYDIN