Patents Assigned to ASELSAN ELEKTRONIK SANAYI VE TICARET A.S.
  • Patent number: 10566623
    Abstract: Batteries and methods of forming the same include a lithium anode, an electrolyte having a high solubility for lithium ions and oxygen, and a thin graphene cathode formed on a substrate. Lithium ions migrate from the lithium anode through the electrolyte to form Li2O2 at a surface of the thin graphene cathode.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: February 18, 2020
    Assignees: ASELSAN ELEKTRONIK SANAYI VE TICARET A.S, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Esin Akca, Cagla Akgun, Gokhan Demirci, Damon B. Farmer, Shu-Jen Han, Hareem T. Maune, Dahyun Oh
  • Patent number: 10478087
    Abstract: An open bore coil system enabling electronic steering and rotation of a Field Free Line (FFL) inside a large volume. An FFL is generated by placing two parallel coil pairs (fed with alternating current directions) side by side. Using two of these coil groups, the FFL can be rotated in the plane perpendicular to the coil axes. The FFL can be translated in the rotation plane of the FFL using a coil pair placed on the same axis with the other coils. It can also be translated in the perpendicular plane by asymmetrical coil excitation. As all the coils in the system are parallel, the imaged object can be reached from the sides during imaging.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: November 19, 2019
    Assignee: ASELSAN ELEKTRONIK SANAYI VE TICARET A.S.
    Inventors: Can Baris Top, Huseyin Emre Guven
  • Patent number: 10110237
    Abstract: A detection system and a detection method for detecting the loss of lock between a PLL reference clock signal and a PLL feedback clock signal. The detection system includes a pseudorandom bit sequence generator; a first shift register; a second shift register; a third shift register; a first synchronizer; a second synchronizer; a third synchronizer; a first comparator; a second comparator; and an alarm control unit. The method comprises the steps of, generating an n-bit wide pseudorandom bit sequence; sampling the sequence with PLL reference clock signal, PLL feedback clock signal and inverse of PLL feedback clock signal; re-sampling and re-synchronizing the sampled sequences; comparing re-sampled and re-synchronized sequence, previously sampled with PLL reference clock signal, with re-sampled and re-synchronized sequences, previously sampled PLL feedback clock signal and inverse of PLL feedback clock signal; generating a flag signal if the comparisons give no match.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: October 23, 2018
    Assignee: ASELSAN ELEKTRONIK SANAYI VE TICARET A.S.
    Inventors: Asim Kepkep, Emre Apaydin
  • Publication number: 20180231629
    Abstract: An open bore coil system enabling electronic steering and rotation of a Field Free Line (FFL) inside a large volume. An FFL is generated by placing two parallel coil pairs (fed with alternating current directions) side by side. Using two of these coil groups, the FFL can be rotated in the plane perpendicular to the coil axes. The FFL can be translated in the rotation plane of the FFL using a coil pair placed on the same axis with the other coils. It can also be translated in the perpendicular plane by asymmetrical coil excitation. As all the coils in the system are parallel, the imaged object can be reached from the sides during imaging.
    Type: Application
    Filed: February 16, 2017
    Publication date: August 16, 2018
    Applicant: ASELSAN ELEKTRONIK SANAYI VE TICARET A.S.
    Inventors: CAN BARIS TOP, Huseyin Emre Guven
  • Publication number: 20180054207
    Abstract: A detection system and a detection method for detecting the loss of lock between a PLL reference clock signal and a PLL feedback clock signal. The detection system includes a pseudorandom bit sequence generator; a first shift register; a second shift register; a third shift register; a first synchronizer; a second synchronizer; a third synchronizer; a first comparator; a second comparator; and an alarm control unit. The method comprises the steps of, generating an n-bit wide pseudorandom bit sequence; sampling the sequence with PLL reference clock signal, PLL feedback clock signal and inverse of PLL feedback clock signal; re-sampling and re-synchronizing the sampled sequences; comparing re-sampled and re-synchronized sequence, previously sampled with PLL reference clock signal, with re-sampled and re-synchronized sequences, previously sampled PLL feedback clock signal and inverse of PLL feedback clock signal; generating a flag signal if the comparisons give no match.
    Type: Application
    Filed: June 20, 2017
    Publication date: February 22, 2018
    Applicant: ASELSAN ELEKTRONIK SANAYI VE TICARET A.S.
    Inventors: Asim KEPKEP, Emre APAYDIN