Patents Assigned to Ashutosh Das
  • Clock guided logic with reduced switching
    Patent number: 8102189
    Abstract: Methods and apparatuses for optimizing switching delay in integrated circuits are described. Combinational logic gates are modified with precharge circuitry and instantiated in order to reduce switching transitions of circuit elements in a signal path.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: January 24, 2012
    Assignee: Ashutosh Das
    Inventor: Ashutosh Das