Abstract: The pixel capacitances of an LCD array can be inspected easily and in a short time without being affected by the capacitance of the tester system. On the first occasion, pixel capacitance CP is charged with pixel voltage VP and line capacitance CS (CS>>CP) that is connected in parallel with pixel capacitance CP is charged with set voltage VS (VP≠VS). By connecting pixel capacitance CP and line capacitance CS is parallel, the difference voltage &Dgr;VS1 of the voltage of the line capacitance CS after the parallel connection and the set voltage VS that is charged thereon before the parallel connection is measured. On the second occasion, pixel capacitance CP is charged with pixel voltage VP and a known reference capacitance &Dgr;CS is connected in parallel with line capacitance CS, this being charged with set voltage VS.

Abstract: A semiconductor memory testing apparatus of the present invention includes a signal generating unit for generating an input signal, an address signal and an expected value signal, a judging unit for judging a quality by comparing the output signal outputted by a semiconductor memory device under test with the expected value signal and generating a judgement signal, and a defect analyzing memory unit having a defect analyzing memory for storing the judgement signal. An address space of the address signal generated by the signal generating unit is set according to classification of the memory cells of the semiconductor memory device under test, and the signal generating unit includes an address space switching unit for switching over the address space as the necessity may arise. The defect analyzing memory unit sets a predetermined address in accordance with the address space to which the address signal belongs.

Abstract: When defective bits of a memory are remedied, the disclosed memory analyzing apparatus can execute remedy analysis of a large capacity memory freely and effectively in a short time. Data are transferred from a defect cell memory (3) provided for a memory tester body (1) to a remedy analyzing apparatus (2) in the sequence suitable for defect remedy. The transferred data are regenerated in address sequence, and the numbers of the defective bits are counted and stored in an X line defect memory (26) and a Y line defect memory (27) at the same time. Further, a line detect flag is raised on the basis of the number of detective bits in the same row and the same column. Further, with respect to the defective bits of a line other than the defect line, the addresses thereof are stored in the bit defect memory (35), and the number of the defect bits is stored in a unit region defect number memory (33) for each defect remedy unit region.