Abstract: A hybrid serial peripheral interface (SPI) data transmission architecture adapted in a network device for connecting a host and a network is provided. The architecture comprises a RX buffer and RX SPI for maintaining a data receiving process, a TX buffer and TX SPI for maintaining a data transmission process, a configuration and status register and a hybrid SPI processing module. The hybrid SPI processing module makes the RX SPI performs the data transmission process as well when the RX SPI idles and the data transmission process proceeds at the same time and makes the TX SPI to performs the data receiving process as well when the TX SPI idles and the data receiving process proceeds at the same time. A hybrid SPI data transmission method is disclosed herein as well.

Abstract: The invention relates to a virtual processor through USB (VPTU), which is installed in a peripheral with USB interface specifications and comprises an I/O instruction decoding unit for decoding or compiling received and compiled instructions of USB packets for parsing the instructions and converting the same into instructions identifiable by an application chipset of the peripheral or a CPU of a computer in order to eliminate microprocessors and memory devices of a conventional peripheral complied with the USB interface specifications and perform operations involved in the transmission or receiving of the USB packets and storing USB interface programs and intermediate data created in the operations.

Abstract: The invention relates to a virtual I/O device coupled to a memory controller in a microprocessor of computer, the virtual I/O device and a memory unit being in communication with the memory controller via a common interface so that any of a plurality of peripherals is capable of coupling to an arithmetic and logic unit (ALU) in the microprocessor via the virtual I/O device and the memory controller sequentially, and an excessive time spent on a processing of request and acknowledgement in handshake while packets being received or transmitted between a conventional I/O device and the I/O interface in the microprocessor is significantly reduced.