Abstract: This invention relates to a single-chip USB-to-Ethernet controller that can operate either as a standalone USB-to-Ethernet controller integrated circuit chip in one mode, or the Ethernet PHY or the USB-to-Rev-MII Bridging chip in another mode, namely Dual-PHY mode, to interface with an external Network Microcontroller's Ethernet MAC for providing Ethernet and USB Device interface in a network communication system and to provide a mechanism for auto-detection and auto-selection between the Ethernet interface and USB Device interface through some Station Management Register access wherein the Network Microcontroller's Ethernet MAC can access two PHY devices through the same Station Management Interface.

Abstract: This invention relates to an advanced system and method of reprogrammable boot codes and In Application Programming (IAP) of embedded systems by booting up with boot loader to shadow program codes on to an internal high speed SRAM and extending contiguously to external higher space memory for runtime applications, and supporting on-line IAP to update run-time firmware or boot loader driver through network communication by utilizing advanced address remapping scheme as well as supporting In System Programming (ISP) to program initial Flash memory via ISP adaptor.

Abstract: The present invention discloses a reprogrammable built-in-self-test integrated circuit and a test method for the same, wherein test programs are directly stored in the application program memory of the logic chip of a SoC IC, and an external test apparatus is used to load the test programs into the application program memory via a serial transmission interface, and an application CPU is used to read and execute the test programs to perform the bonding-wire connectivity between the logic chip and the memory chip. In the present invention, test vectors can still be flexibly revised after tapeout to increase test coverage. As the test programs are directly stored in the existing application program memory without using additional memory space, and as the test programs are executed by the existing application CPU without using an extra built-in-self-test circuit, the present invention can effectively reduce test cost.

Abstract: The present invention is to provide a burst transfer mechanism of network packets having MAC frames over USB bus, which is designed in an Application Specific Integrated Circuit (ASIC) being installed in a USB compliant networking device, enabling the networking device to assemble a plurality of Ethernet network packets having MAC frames together as a super-size network packet and, while receiving a Bulk In/Out request packet, transfer the super-size network packet into a plurality of USB packets having maximum packet size defined for the USB endpoint, and transmit the USB packets out within a burst cycle of Bulk In/Out transaction, in order to greatly improve and enhance the throughput performance of the network packets over USB bus.

Abstract: The present invention is to provide a burst transfer mechanism of network packets having MAC frames over USB bus, which is designed in an Application Specific Integrated Circuit (ASIC) being installed in a USB compliant networking device, enabling the networking device to assemble a plurality of Ethernet network packets having MAC frames together as a super-size network packet and, while receiving a Bulk In/Out request packet, transfer the super-size network packet into a plurality of USB packets having maximum packet size defined for the USB endpoint, and transmit the USB packets out within a burst cycle of Bulk In/Out transaction, in order to greatly improve and enhance the throughput performance of the network packets over USB bus.

Abstract: The invention relates to a virtual I/O device coupled to a memory controller in a microprocessor of computer, the virtual I/O device and a memory unit being in communication with the memory controller via a common interface so that any of a plurality of peripherals is capable of coupling to an arithmetic and logic unit (ALU) in the microprocessor via the virtual I/O device and the memory controller sequentially, and an excessive time spent on a processing of request and acknowledgement in handshake while packets being received or transmitted between a conventional I/O device and the I/O interface in the microprocessor is significantly reduced.

Abstract: The invention relates to a virtual processor through USB (VPTU), which is installed in a peripheral with USB interface specifications and comprises an I/O instruction decoding unit for decoding or compiling received and compiled instructions of USB packets for parsing the instructions and converting the same into instructions identifiable by an application chipset of the peripheral or a CPU of a computer in order to eliminate microprocessors and memory devices of a conventional peripheral complied with the USB interface specifications and perform operations involved in the transmission or receiving of the USB packets and storing USB interface programs and intermediate data created in the operations.