Patents Assigned to ASM-Nutool Inc.
  • Patent number: 7625814
    Abstract: A method of filling a conductive material in a three dimensional integration feature formed on a surface of a wafer is disclosed. The feature is optionally lined with dielectric and/or adhesion/barrier layers and then filled with a liquid mixture containing conductive precursor, such as a solution with dissolved ruthenium precursor or a dispersion or suspension with conductive particles (e.g., gold, silver, copper), and the substrate is rotated while the mixture is on its surface. Then, the liquid carrier is dried from the feature, leaving a conductive layer in the feature. These two steps are optionally repeated until the feature is filled up with the conductor. Then, the conductor is annealed in the feature, thereby forming a dense conductive plug in the feature.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: December 1, 2009
    Assignee: ASM Nutool, Inc.
    Inventors: Ismail Emesh, Chantal J. Arena, Bulent M. Basol
  • Publication number: 20090065365
    Abstract: A method and apparatus for a copper electroplating procedure, wherein a first additive is preferentially adsorbed onto the field region of a substrate and a second additive is preferentially adsorbed onto the surfaces of at least one recessed region of the substrate, is provided. The first additive is more resistive to the electrodeposition relative to the second additive such that the recessed regions are filled at a faster rate than a layer is deposited on the field region.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 12, 2009
    Applicant: ASM NUTOOL, INC.
    Inventors: Ayse Durmus, Ismail Emesh
  • Patent number: 7485561
    Abstract: A method of filling a conductive material in a three dimensional integration structure feature formed on a surface of a wafer is disclosed. The feature is filled with a dispersion containing a plurality of conductive particles and a solvent. Then, the solvent is removed from the feature, leaving the plurality of conductive particles in the feature. These two steps are repeated until the feature is filled up with the conductive particles. Then, the conductive particles are annealed in the feature, thereby forming a dense conductive plug in the feature.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: February 3, 2009
    Assignee: ASM NuTool, Inc.
    Inventor: Bulent M. Basol
  • Publication number: 20080242078
    Abstract: A method for filling defect-free conductive material in deep vias or cavities in semiconductor wafers in 3-D integration structures is provided. The process may be performed in at least two steps for depositing the conductive material, including a first deposition step that partially fills the cavity with the conductive material and forms a conformal layer, which may also reduce the depth and width of the cavity, and a second deposition step that completely fills the same conductive material into the space defined by the conformal layer.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicant: ASM NUTOOL, INC.
    Inventors: Hessel Sprey, Hyung-Sang Park
  • Publication number: 20070293040
    Abstract: A method of filling a conductive material in a three dimensional integration feature formed on a surface of a wafer is disclosed. The feature is optionally lined with dielectric and/or adhesion/barrier layers and then filled with a liquid mixture containing conductive precursor, such as a solution with dissolved ruthenium precursor or a dispersion or suspension with conductive particles (e.g., gold, silver, copper), and the substrate is rotated while the mixture is on its surface. Then, the liquid carrier is dried from the feature, leaving a conductive layer in the feature. These two steps are optionally repeated until the feature is filled up with the conductor. Then, the conductor is annealed in the feature, thereby forming a dense conductive plug in the feature.
    Type: Application
    Filed: April 30, 2007
    Publication date: December 20, 2007
    Applicant: ASM NUTOOL, INC.
    Inventors: Ismail Emesh, Chantal Arena, Bulent Basol
  • Publication number: 20070131563
    Abstract: An electrochemical mechanical process for electroplating or electropolishing a conductive surface of a wafer is provided. The conductive surface of the wafer is touched by a polishing surface of a compressible pad while a process solution flows through the pad and a potential difference is maintained between the conductive surface and an electrode. The pressure between the polishing surface and a central region of the conductive surface is increased by applying a shaping process to either the conductive surface or the pad.
    Type: Application
    Filed: November 28, 2006
    Publication date: June 14, 2007
    Applicant: ASM NUTOOL, INC.
    Inventors: Jeffrey Bogart, Bulent Basol
  • Patent number: 7189146
    Abstract: The present invention provides a method and apparatus for wet processing of a conductive layer using a degassed process solution such as a degassed electrochemical deposition solution, a degassed electrochemical polishing solution, a degassed electroless deposition solution, and a degassed cleaning solution. The technique includes degassing the process solution before delivering the degassed process solution to a processing unit or degassing the process solution in-situ, within the processing unit.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: March 13, 2007
    Assignee: ASM Nutool, Inc.
    Inventors: Bulent M. Basol, Cyprian E. Uzoh
  • Patent number: 7172497
    Abstract: A system and a method of forming copper interconnect structures in a surface of a wafer is provided. The method includes a step of performing a planar electroplating process in an electrochemical mechanical deposition station for filling copper material into a plurality of cavities formed in the surface of the wafer. The electroplating continues until a planar layer of copper with a predetermined thickness is formed on the surface of the wafer. In a following chemical mechanical polishing step the planar layer is removed until the copper remains in the cavities, insulated from one another by exposed regions of the dielectric layer.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: February 6, 2007
    Assignee: ASM Nutool, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh
  • Patent number: 7147766
    Abstract: The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: December 12, 2006
    Assignee: ASM NuTool, Inc.
    Inventors: Cyprian Emeka Uzoh, Homayoun Talieh, Bulent Basol
  • Patent number: 7141146
    Abstract: An electrochemical mechanical process for electroplating or electropolishing a conductive surface of a wafer is provided. The conductive surface of the wafer is touched by a polishing surface of a compressible pad while a process solution flows through the pad and a potential difference is maintained between the conductive surface and an electrode. The pressure between the polishing surface and a central region of the conductive surface is increased by applying a shaping process to either the conductive surface or the pad.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: November 28, 2006
    Assignee: ASM Nutool, Inc.
    Inventors: Jeffrey Bogart, Bulent M. Basol
  • Patent number: 7129165
    Abstract: A method of forming a conductor structure on a surface of a wafer is provided. The surface of the wafer includes cavities separated by field regions. Initially, a barrier layer is deposited on the surface that includes cavities separated by field regions. A thin seed layer with a substantially uniform thickness is deposited on the barrier layer. The barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity. The remaining volume of each cavity is filled with a conductive material which is formed on the seed layer. The conductive layer has a substantially small thickness. After forming the conductive layer, the wafer is annealed to increase grain size in the conductive layer and the seed layer.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: October 31, 2006
    Assignee: ASM Nutool, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh
  • Patent number: 7122473
    Abstract: The present invention provides at least one nozzle that sprays a rotating workpiece with an etchant at an edge thereof. The at least one nozzle is located in an upper chamber of a vertically configured processing subsystem that also includes mechanisms for plating, cleaning and drying in upper and lower chambers.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: October 17, 2006
    Assignee: ASM Nutool, Inc.
    Inventors: Jalal Ashjaee, Rimma Volodarsky, Cyprian E. Uzoh, Bulent M. Basol, Homayoun Talieh
  • Patent number: 7115510
    Abstract: The present invention relates to a process for forming a near-planar or planar layer of a conducting material, such as copper, on a surface of a workpiece using an ECMPR technique. The process preferably uses at least two separate plating solution chemistries to form a near-planar or planar copper layer on a semiconductor substrate that has features or cavities on its surface.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: October 3, 2006
    Assignee: ASM Nutool, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh, Cyprian E. Uzoh
  • Patent number: 7101471
    Abstract: An electroetching process of the present invention uses a multiphase environment for planarizing a wafer with conductive surface having a non-uniform topography. The multiphase environment includes a high resistance phase and an etching solution phase. The conductive surface to be planarized is placed in the high resistance phase and adjacent a phase interface between the high resistance phase and the etching solution phase. A wiper is used to mechanically move the thin high resistance phase covering the conductive surface so that the raised regions of the non-planar conductive surface is briefly exposed to etching solution phase. The mechanical action of the wiper does not disturb the high resistivity phase filling the rescessed regions of the surface. As the raised surface locations are exposed, the etching solution phase contacts and electroetch the exposed regions of the raised regions until the surface planarized.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: September 5, 2006
    Assignee: ASM Nutool, Inc.
    Inventor: Erol C. Basol
  • Patent number: 7097538
    Abstract: The methods and systems described provide for an in-situ endpoint detection for material removal processes such as chemical mechanical polishing (CMP) performed on a workpiece. In a preferred embodiment, an optical detection system is used to detect endpoint during the removal of planar conductive layers using CMP. An optically transparent polishing belt provides endpoint detection through any spot on the polishing belt. Once endpoint is detected, a signal can be used to terminate or alter a CMP process that has been previously initiated.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: August 29, 2006
    Assignee: ASM NuTool, Inc.
    Inventors: Homayoun Talieh, Bulent M. Basol
  • Patent number: 7097755
    Abstract: The present invention provides an apparatus for electrochemical mechanical processing of a surface of a workpiece by utilizing a process solution. The apparatus of the present invention includes an electrode touching the process solution, a belt workpiece surface influencing device extended between a supply spool and a receiving spool. During the process, the surface of the workpiece is placed in proximity of the workpiece surface influencing device and the process solution is flowed through the process section and onto the surface while a potential difference is applied between the electrode and the surface of the workpiece.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: August 29, 2006
    Assignee: ASM Nutool, Inc.
    Inventors: Bulent M. Basol, Halit N. Yakupoglu, Cyprian E. Uzoh, Homayoun Talieh
  • Patent number: 7064057
    Abstract: An apparatus for electropolishing a conductive material layer is disclosed. The apparatus comprises a porous conductive member configured to contact the conductive layer and having a first connector for receiving electrical power, an electrode insulatively coupled to the porous conductive member having a second connector configured to receive electrical power, a holder insulatively coupled to the porous conductive member and the electrode configured to establish relative motion between the porous conductive member and the conductive layer, and a power supply coupled to the first connector and the second connector configured to supply the electrical power between the electrode and the porous conductive member for electropolishing the conductive layer.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: June 20, 2006
    Assignee: ASM Nutool, Inc.
    Inventor: Bulent M. Basol
  • Patent number: 7059944
    Abstract: An integrated process tool for chemical mechanical processing, cleaning and drying a semiconductor workpiece is provided. The integrated process tool includes a CMP module and a cleaning and drying module. After being processed, the workpiece is transported from the CMP module to the cleaning and drying module using a movable housing. In the cleaning and drying module, a cleaning mechanism is used to clean the workpiece while the workpiece is rotated and held by a support stucture of the movable housing. A drying mechanism of the cleaning and drying module picks up the workpiece from the moveable housing and spin dries it. Throughout the CMP process, cleaning and drying, the processed surface of the wafer faces down.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: June 13, 2006
    Assignee: ASM Nutool, Inc.
    Inventors: Jalal Ashjaee, Boris Govzman, Bernard M. Frey, Boguslaw A. Nagorski, Douglas W. Young, Bulent M. Basol, Homayoun Talieh
  • Patent number: 7045040
    Abstract: A method and system for preventing gas bubble formation on a selected region of a wafer surface as the surface is brought in contact with a process solution for an electrochemical process is provided. The present invention employs the process solution to prevent or remove gas bubbles from the wafer surface during or before the electrochemical processing of the wafer surface. Accordingly, during the process, the wafer surface is initially brought in proximity of the surface of the process solution. Next, a process solution flow is directed towards the selected region of the wafer surface for a predetermined time. In the following step, the selected region of the wafer surface is contacted with the process solution flow for the predetermined time to prevent bubble formation, and the wafer surface is immersed into the process solution for electrochemical processing.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: May 16, 2006
    Assignee: ASM Nutool, Inc.
    Inventor: Bulent M. Basol
  • Patent number: 7029567
    Abstract: An edge cleaning system and method is disclosed in which a directed stream of a mild etching solution is supplied to an edge area of a rotating workpiece, including the front surface edge and bevel, while a potential difference between the workpiece and the directed stream is maintained. In one aspect, the present invention provides an edge cleaning system that is disposed in the same processing chamber that is used for deposition or removal processing of the workpiece. In another aspect, the mild etching solution used for edge removal is also used to clean the front surface of the wafer, either simultaneously with or sequentially with the edge removal process.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: April 18, 2006
    Assignee: Asm Nutool, Inc.
    Inventor: Bulent M. Basol