Abstract: A testing system and a testing method are provided. The testing system includes a first testing device and a second testing device. The first testing device is coupled to a first stream facing-port of a device under test (DUT). The first testing device includes a controller. The second testing device is coupled to a second stream facing-port of the DUT. The controller transmits a testing signal to the DUT through the first stream facing-port to test a universal serial bus (USB) of the DUT. The DUT is operated based on the testing signal to generate a data signal. The DUT outputs the data signal to the second testing device through the second stream facing-port. The second testing device obtains status information of the DUT which is operated based on the testing signal to generate a testing result. The controller determines whether the DUT is normal according to the testing result.

Abstract: A testing circuit for testing a universal serial bus (USB) of an electronic device includes a controller, a first switch, a pull-down resistor, a gating pull-up resistor, and a second switch. The controller provides a control signal according to a power receiving condition of the electronic device. A control terminal of the first switch is coupled to the controller. The pull-down resistor is coupled between a configuration channel pin of the USB and a first terminal of the first switch. The gating pull-up resistor is coupled between the configuration channel pin and the control terminal of the first switch. A control terminal of the second switch is coupled to the controller. A first terminal of the second switch is coupled to a second terminal of the first switch and a ground pin of the USB. A second terminal of the second switch is coupled to a reference low voltage.

Abstract: A testing system and a testing method are provided. The testing system includes a first testing device and a second testing device. The first testing device is coupled to a first stream facing-port of a device under test (DUT). The first testing device includes a controller. The second testing device is coupled to a second stream facing-port of the DUT. The controller transmits a testing signal to the DUT through the first stream facing-port to test a universal serial bus (USB) of the DUT. The DUT is operated based on the testing signal to generate a data signal. The DUT outputs the data signal to the second testing device through the second stream facing-port. The second testing device obtains status information of the DUT which is operated based on the testing signal 10 to generate a testing result. The controller determines whether the DUT is normal according to the testing result.

Abstract: A testing circuit for testing a universal serial bus (USB) of an electronic device includes a controller, a first switch, a pull-down resistor, a gating pull-up resistor, and a second switch. The controller provides a control signal according to a power receiving condition of the electronic device. A control terminal of the first switch is coupled to the controller. The pull-down resistor is coupled between a configuration channel pin of the USB and a first terminal of the first switch. The gating pull-up resistor is coupled between the configuration channel pin and the control terminal of the first switch. A control terminal of the second switch is coupled to the controller. A first terminal of the second switch is coupled to a second terminal of the first switch and a ground pin of the USB. A second terminal of the second switch is coupled to a reference low voltage.

Abstract: A differential amplifier circuit is provided. The differential amplifier circuit includes a differential amplifier, a first active inductor, a second active inductor, and a parameter circuit. The differential amplifier includes a first differential output terminal and a second differential output terminal. The first active inductor is coupled to the first differential output terminal. The second active inductor is coupled to the second differential output terminal. The parameter circuit is coupled between the first active inductor and the second active inductor. The parameter circuit provides at least one parameter. A low frequency gain, an equivalent impedance, and a bandwidth of the differential amplifier circuit are adjusted in response to the at least one parameter.

Abstract: A transmission circuit is provided. The transmission circuit includes a T-coil, a first resistance value generator, a second resistance value generator and a capacitance value generator. The first resistance value generator generates a first resistance value according to a first control signal. The second resistance value generator generates a second resistance value according to a second control signal. The capacitance value generator generates a capacitance value according to a third control signal. A gain spectrum of the transmission circuit is adjusted according to the first resistance value, the second resistance value and the capacitance value.

Abstract: A transmission circuit is provided. The transmission circuit includes a T-coil, a first resistance value generator, a second resistance value generator and a capacitance value generator. The first resistance value generator generates a first resistance value according to a first control signal. The second resistance value generator generates a second resistance value according to a second control signal. The capacitance value generator generates a capacitance value according to a third control signal. A gain spectrum of the transmission circuit is adjusted according to the first resistance value, the second resistance value and the capacitance value.

Abstract: A data storage apparatus and a data prediction method thereof are provided. The data storage apparatus includes a memory unit and a prediction unit. The prediction unit acquires a plurality of access location data of a plurality of data access actions of a prior access history of the memory unit. The prediction unit analyzes the prior access history of the memory unit. The prediction unit performs a quantification process on the access location data to acquire a plurality of quantized data corresponding to the prior access history. The prediction unit predicts a data pre-accessing target of the memory unit according to the quantized data.

Abstract: A management method for a data storage device is provided and includes the following steps: obtaining a plurality of association rules according to a plurality of previous access commands; building a plurality of look-up tables according to the association rules; receiving a current access command and determining whether the current access command corresponds to at least one of the look-up tables to obtain physical addresses of the current access command from the corresponding look-up table; predicting a look-up table corresponding to a subsequent access command based on these association rules; and pre-establishing the predicted look-up tables. The invention also provides a data storage system and a data storage device, which can implement the management method described above.

Abstract: A data storage apparatus and a data prediction method thereof are provided. The data storage apparatus includes a memory unit and a prediction unit. The prediction unit acquires a plurality of access location data of a plurality of data access actions of a prior access history of the memory unit. The prediction unit analyzes the prior access history of the memory unit. The prediction unit performs a quantification process on the access location data to acquire a plurality of quantized data corresponding to the prior access history. The prediction unit predicts a data pre-accessing target of the memory unit according to the quantized data.

Abstract: An eye diagram observation device is provided. The eye diagram observation device includes an eye diagram determination circuit and a clock generator. The eye diagram determination circuit obtains an eye diagram corresponding to an input signal pair based on a delayed sampling clock. The clock generator includes a voltage to time converter (VTC). The VTC generates a delayed clock based on a voltage value of an input voltage. The clock generator generates the delayed sampling clock based on the delayed clock. The eye diagram observation device may reduce power consumption and a layout area via the VTC.

Abstract: An electronic device comprising a mainboard and a device is provided. The mainboard includes a first storage circuit, a CPU circuit and a data transmission interface circuit. The first storage circuit is configured to store a first firmware code of a basic input/output system, the CPU circuit is coupled to the first storage circuit, the CPU circuit is configured to execute the first firmware code to run the basic input/output system, and the data transmission interface circuit is coupled to the CPU circuit. The device is coupled to the data transmission interface circuit of the mainboard for providing a device function to the CPU circuit via the data transmission interface circuit. The device includes a controller, the controller includes a second storage circuit, a microcontroller and a suspend power register. An operation method of the electronic device is also provided.

Abstract: An electronic device comprising a mainboard and a device is provided. The mainboard includes a first storage circuit, a CPU circuit and a data transmission interface circuit. The first storage circuit is configured to store a first firmware code of a basic input/output system, the CPU circuit is coupled to the first storage circuit, the CPU circuit is configured to execute the first firmware code to run the basic input/output system, and the data transmission interface circuit is coupled to the CPU circuit. The device is coupled to the data transmission interface circuit of the mainboard for providing a device function to the CPU circuit via the data transmission interface circuit. The device includes a controller, the controller includes a second storage circuit, a microcontroller and a suspend power register. An operation method of the electronic device is also provided.

Abstract: An electronic apparatus including a central processing unit (CPU), a chipset, a first interface circuit, a temporary memory, a BIOS (basic input/output system) memory, a second interface circuit and a first switcher is provided. The chipset is coupled to the CPU and the first switcher. The temporary memory is coupled to the first switcher and the first interface circuit. The first interface circuit is coupled to the electronic apparatus and an extended storage including a first BIOS. The second interface circuit is coupled to the first switcher and the BIOS memory. If the first BIOS is stored in the temporary memory, the temporary memory is coupled to the chipset by the first switcher; if the first BIOS is not stored in the temporary memory, the second interface circuit is coupled to the chipset by the first switcher. The electronic device can safely updates the BIOS.

Abstract: A system-on-chip (SoC) and a booting method thereof are disclosed. The SoC is coupled to an external memory and includes a read only memory (ROM) and a processor. The ROM stores a first firmware image. The processor is coupled to the ROM. The processor reads the first firmware image from the ROM and verifies the state of the first firmware image. If the first firmware image is damaged, the processor reads a second firmware image from the external memory and verifies whether the second firmware image is legal. If the verification of the second firmware image succeeds, the processor reads and executes the second firmware image to perform a booting process.

Abstract: An electronic system and an operating method thereof are provided. When a computer host is booting up and an external storage device is connected with the computer host, the BIOS of the computer host may read the parameter information recorded in a memory of a bridge unit via a bridge unit of the external device and displays the parameter information without initializing the storage unit and reading the parameter information from a magnetic region of the storage unit.

Abstract: A high-definition multimedia interface (HDMI) data transceiving apparatus is disclosed. The HDMI data transceiving apparatus includes a data receiver and a data transmitter. The data transmitter includes a first impedance-providing device and a second impedance-providing device. The data transmitter has a first data transmission terminal and a second data transmission terminal. The first data transmission terminal and the second data transmission terminal are coupled to the data receiver through a first transmission line and a second transmission line, respectively. The data transmitter respectively transmits first data and second data to the data receiver. The first impedance-providing device and the second impedance-providing device absorb a reflected wave generated by the HDMI data transceiving apparatus when the first data and the second data are transmitted.

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system includes a first disk and a second disk The data processing method includes: receiving a reading command, wherein the reading, command includes a data starting address; determining to assign the reading command to the first disk or the second disk according to the data starting address of the reading command. and a stripe size; and reading corresponding data according to the reading command from the first disk or the second disk which receives the reading command.

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system is a redundancy array of independent disk 0 (RAID 0) system The disk array system includes a plurality of disks. The data processing method includes: receiving a reading command; determining whether to divide the reading command to a plurality of reading command segments according to the reading command; and assigning the reading command to a corresponding disk of the disks to read data stored in the corresponding disk accordingly when it is determined that the reading command is not divided.

Abstract: An electronic device comprises a first memory unit, a processing unit and an operating interface. The processing unit is electronically connected to the first memory unit. The operating interface is electronically connected to the processing unit. When the processing unit is communicated with a host device via the operating interface, the processing unit executes a loading program and transmits a notification signal to the host device. The host device transmits at least one control program to the first memory unit according to the notification signal. When the control program is transmitted, the processing unit is reset and then executes the control program stored in the first memory unit. The stored firmware can be added or modified, and the circuit layout is simplified.