Abstract: Distributed antenna systems (DAS) and methods are disclosed that are aware of cellular user/antenna relationships. The DAS systems and/or methods include or use one or more User Aware Units that provide the functionality of knowing (or, knowledge of) which cellular user(s) each antenna can communicate with (and vice versa). The User Aware Unit functions to gather information about the reception in each antenna in order to identify the cellular users that the respective antenna can communicate with or best communicate with compared to other cellular users.

Abstract: Systems, methods, and software can provide high-accuracy position estimation for mobile user equipment (UE) configured for use within a service area covered by a plurality of radio units, e.g., O-RUs, with known position including coordinates. A channel estimate can be derived for a channel between a given UE and each of a plurality of radio units based on a sounding reference signal (SRS) received from the UE and used to select a subset of the radio units. The shortest delay can be calculated for the given UE to each O-RU in the subset, forming a set of uplink-time-difference-of-arrival (UL-TDOA) measurements; position of the given UE in the service area can be estimated based on the UL-TDOA measurements. The O-RU synchronization error can be estimated for each O-RU in the subset using estimated positions of the given UE and corresponding UL-TDOA measurements.

Abstract: Distributed antenna systems (DAS) and methods are disclosed that are aware of cellular user/antenna relationships. The DAS systems and/or methods include or use one or more User Aware Units that provide the functionality of knowing (or, knowledge of) which cellular user(s) each antenna can communicate with (and vice versa). The User Aware Unit functions to gather information about the reception in each antenna in order to identify the cellular users that the respective antenna can communicate with or best communicate with compared to other cellular users.

Abstract: A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.

Abstract: A chip architectural core is described for use in decoding one or more vectors received by the core in accordance with one or more recursive and/or non-recursive systematic trellis codes of varying sizes and constraints K, as well as generator polynomials. The core comprises: a decoder including (a) a reconfigurable network of ACS blocks, BMU generators and trace-back mechanisms for both recursive and non-recursive systematic forms, and (b) reconfigurable connections between the ACS blocks, BMU generators and trace-back mechanisms, arranged so that the precise number of network components can be continuously rearranged and interconnected in a network as a function of size and the constraint K and generator polynomial of each code used for encoding the vectors received by the core.

Abstract: A reconfigurable architecture for and method of performing a fast orthogonal transform of vectors in multiple stages, the size of a vector being N, wherein N can vary and the number of stages is a function of N, the architecture comprising: a computational unit configured and arranged so as to include one or more butterfly units; a block including one or more multipliers coupled to the output of the computational unit, configured and arranged so as to perform all of the butterfly computations for at least one stage of the transform; a storage unit configured and arranged so as to store the intermediate results of the butterfly computations and predetermined coefficients for use by the computational unit for performing each butterfly computation, the storage unit including memory and multiplexing architecture; the storage unit including memory and multiplexing architecture; a multiplexer unit configured and arranged so as to time multiplex all of the butterfly computations of the transform using said comput

Abstract: An apparatus and method for control in a reconfigurable architecture is shown and described. In one example, an integrated circuit configured to implement a plurality of communications standards includes a plurality of upper level controllers and a plurality of lower level controllers. The upper level controller are configured to operate according to a portion of a communications standard and implement upper level control functions for the associated standard. The low level controllers are capable of communicating with each of the upper level controllers and can be assigned to each of the upper level controls to implement low level functions of each of the plurality of communications standards.

Abstract: A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.