Abstract: A biodegradable plant container made from a cellulosically derived polymer is coated with an enhancer to facilitate biodegradation of the container.

Abstract: A method executed by an instruction set on a processor is described. The method includes providing a tbbit instruction, inputting a first index for the tbbit instruction, loading a second value for the tbbit instruction, wherein the second value comprises at least 2b bits, using selected b bits of the first index to select at least one target bit in the loaded second value, shifting the target bit into the bottom of the first index, and computing a second index based on the shifting of the target bit into the bottom of the first index. Other methods and variations are also described.

Abstract: A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

Abstract: A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

Abstract: A method which determines by an optimizing compiler whether any variable in the given program equals to the given acyclic mathematical function applied to given variables in the program and the method includes expressing the bits of the value of the function as a Boolean function of the bits of the inputs and expressing for every variable and statement the value taken by v when s is executed as a Boolean function and expressing, for every statement the condition under which the statement is executed as a Boolean function, and Finally, a determination is made using a Boolean satisfiability oracle of whether, for the given variable and program statement, the a particular Boolean expression holds and a determination is of whether for a given variable and program statement whenever the predicate and the condition are true.

Abstract: A circuit is described including a clock input for at least one clock signal. Only one clock buffer is connected to the clock input to generate, based on the at least one clock signal, at least a first modified clock signal and a second modified clock signal. A plurality of flip-flops are connected to the clock buffer. Each of the flip-flops receive the first and second modified clock signals. A plurality of data inputs are each connected to at least one of the plurality of flip-flops to provide input data to the plurality of flip-flops. A plurality of data outputs each are connected to at least one of the plurality of flip-flops to provide output data from the plurality of flip-flops. Each of the plurality of flip-flops transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal.

Abstract: A method is described for operation of a DMA engine. Copying is initiated for transfer of a first number of bytes from first source memory locations to first destination memory locations. Then, a halt instruction is issued before the first number of bytes are copied. After copying is stopped, a second number of bytes is established, encompassing those bytes remaining to be copied. After the transfer is halted, a quantity of the second number of bytes is identified. Quantity information is then generated and stored. Second source memory locations are identified to indicate where the second number of bytes are stored. Second source memory location information is then generated and stored. Second destination memory locations are then identified to indicate where the second number of bytes are to be transferred. Second destination memory location information is then generated and stored.

Abstract: A processor register file for a multi-threaded processor is described. The processore register file includes, in one embodiment, T threads, having N b-bit wide registers. Each of the registers includes a b-bit master latch, T b-bit slave latches connected to the master latch, and a slave latch write enable connected to the slave latches. The master latch is not opened at the same time as the slave latches. In addition, only one of the slave latches is enabled at any given time. As should be apparent to those skilled in the art, T, N, and b are all integers. Other embodiments and variations are also provided.

Abstract: A method for a Galois Field multiply includes executing first and second instructions. The first instruction includes receiving a first input, such as a first variable, receiving a second input, such as a second variable, performing a polynomial multiplication over GF(2m), using the first and second inputs, and producing a product. The second instruction includes receiving a third input, which may be the product from the first instruction, receiving a fourth input, which is a predetermined generator polynomial to operate upon the product, receiving a fifth input, which is a length of the predetermined generator polynomial, to limit operation of the predetermined generator polynomial upon the product, and computing, via the predetermined generator polynomial limited by the length, a modulus of the product with respect to a divisor. A hardware block is also described.

Abstract: A method of demapping in a receiver including deriving M intermediate soft bit values yj for the I and Q data of the input signal as a function of the spacing in the constellation; and limiting the range of the M values yj. A look-up table index is derived for each of the limited M values yj. A look-up table, having 2N+1 entries for supporting up to N soft bit outputs, is indexed using the derived indices; and K soft bits for each of the M values yj of the I and Q data are outputted.