Abstract: Memory structures are provided, where a fast SRAM in an mNVSRAM block may serve as the buffer for a large block NVM memory to increase the data exchange rate between computing units or processor cores and the large NVM memory. The mNVSRAM blocks may also provide a fast boot function, where a boot code may be stored in the NVM parts of the mNVSRAM block, and due to the high bandwidth communication between fast SRAM part and the associated NVM memories, the boot code may be transferred into the fast SRAM in one or a few clock cycles enabling fast boot up function. Similarly, code stored in the NVM parts of an mNVSRAM block may be transferred into fast SRAM rapidly at wake-up time enabling fast wake up and voiding a need to wake up any other memory part, which may also result in energy savings for the computing system.

Abstract: Technologies for re-configurable non-volatile memory structures and systems for FPGA, as well as, non-volatile static random access memory (nvSRAM) cells with multiple a non-volatile memory (NVM) bits. Proposed structures may quickly switch/reconfigure look-up tables (LUTs) and/or reconfigure FPGA routings. Memory structures according to some embodiments may reduce the switching/reconfiguring times to one or a few clock cycles. Thus, fast or real time FPGA reconfiguration is enabled, one LUT may serve multiple functions, thereby, a fraction of current FPGAs may be used to perform multi-functions, which may substantially reduce FPGA chip areas. Structures according to embodiments may further provide simple routing for entire system by re-configuration and enhanced data security by avoiding external data transmission.

Abstract: Technologies are generally described herein for a hybrid non-volatile memory structure that includes a number of SRAM buffers. SRAM access times may be achieved for non-volatile read/write operations by performing access queue buffered read/write operations first. The SRAM buffer may be shareable as a system SRAM. In other examples, a hybrid non-volatile memory according to some embodiments may include a high speed block and a high endurance block to store different types of data with different access needs. The hybrid non-volatile memory may also include a normal block to store the data which is non-frequently changed.

Abstract: Technologies are generally described herein for static random access memory (SRAM) based memory structures and methods thereof such as multi-bit non-volatile static random-access memory (nvSRAM) with arrayed SRAM and NVM or SRAM buffered one time programmable (OTP) memories, RRAMs or other resistive RAMs.