Abstract: For risk evaluation, a method encodes event data as a linear array that includes a plurality of logic states. The method estimates a success probability for each logic state and identifies path groups of the plurality of logic states. The logic states of each path group must all be healthy for each logic state to contribute to system success. The method further identifies each path combination of path groups and path nodes that result in system success. In addition, the method calculates a system success probability as a sum of success probabilities for each path combination. The success rate for each path combination is calculated as a product of the path group success probabilities for the path combination.

Abstract: For exceptional logic element management, a method encodes a logic design as a linear array that includes a plurality of logic states. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values. The method identifies an exceptional logic element, wherein the exceptional logic element comprises one or more of an exceptional logic state, an exceptional state transition, and an exceptional input combination. In addition, the code displays the plurality of logic states excluding the exceptional logic elements from display.

Abstract: For implementing a logic design, a method encodes a logic design as a linear array that includes a plurality of logic states. The method calculates a combination map for a state transition between a start state and an end state of the plurality of logic states using the linear array to reduce computational overhead. In addition, the method identifies undefined binary input variable transitions for the state transition on the combination map. The method resolves the undefined binary input variable transitions in the linear array. The method generates a final logic design comprising Boolean logic from the linear array with the resolved binary input variable transitions. The method implements the final logic design in hardware by generating semiconductor gates that implement the Boolean logic.

Abstract: For parsing source code into a linear array, a method parses source code into a plurality of logic design elements. The method further identifies conditional logic for each logic design element. In addition, the method identifies computation logic for each logic design element. The method encodes each logic design element as a logic state of a plurality of logic states in a linear array. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values. The method reduces the logic relationships to a Boolean equation. The method generates one of output source code and a hardware implementation from the Boolean equation.

Abstract: For generating path execution times, a method encodes a logic design as a linear array that includes a plurality of logic states. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values. The method iteratively generates a path execution time for each path between a start state and an end state. The method further generates a maximum path execution time between the start state and the end state as a greatest sum of all path execution times between the start state and the end state.

Abstract: For combination map based design, a method defines one or more logic elements including one or more binary output variables and one or more binary input variables. The method further assigns the one or more logic elements to a combination map. In addition, the method defines one or more logic element relationships between the logic elements on the combination map. The method encodes a plurality of fields of the combination map as a linear array that includes a plurality of logic states. Each logic state includes the one or more binary output variables, the one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values.

Abstract: For parsing source code into a linear array, a method parses source code into a plurality of logic design elements. The method further identifies conditional logic for each logic design element. In addition, the method identifies computation logic for each logic design element. The method encodes each logic design element as a logic state of a plurality of logic states in a linear array. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values. The method reduces the logic relationships to a Boolean equation. The method generates one of output source code and a hardware implementation from the Boolean equation.

Abstract: For identifying a nearest connection is disclosed. The method encodes node data as a linear array that includes a plurality of logic states. Each logic state represents a node of node data. The method identifies a valid connection policy for a valid connection element between two logic states of a plurality of logic states. The method further generates a connection element between each two logic states of the plurality of logic states that satisfy the valid connection policy through a combination map. In addition, the method iteratively generates a connection weight sum for each node connection between a start state and an end state. The method further identifies a first node connection between the start state and the end state with a minimum connection weight sum as a nearest node connection.

Abstract: For linear array hierarchy navigation, a method encodes a logic design as a linear array with a plurality of logic states. The method displays combination maps of a plurality of fields at two or more successive display levels having a top display level and at least one lower display level. In addition, the method receives a selection of a first field of the plurality of fields. The method displays the first field and one or more successive combination maps for the first field. Each of the one or more successive combination maps is displayed with a field identifier of a predecessor field. In addition, the method displays relationship arrows linking the first field and each successive field of the first field.

Abstract: For hardware/software agnostic design generation, a method encodes a logic design as a linear array that includes a plurality of logic states. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values. The method generates source code from the plurality of logic states by generating a software structure selected from the group one of a case statement, a table, and a plurality of if/then statements, generating an encoded logic state for each logic state, generating a condition test for each encoded logic state, and appending a binary output variable statement and an assertion indicator value for binary output variable associated with the encoded logic state.

Abstract: For linear array display, a method encodes a logic design as a linear array that includes a plurality of logic states. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values. The method displays the linear array as a combination map comprising a plurality of fields. Each field represents a corresponding logic state.