Abstract: An electronic system having a mounting substrate with a plurality of layers. The mounting substrate combines an upper shield structure and a lower shield structure to form an interlocking shielding structure to reduces crosstalk interference and improve return loss and insertion loss for high-speed serial communication circuits. The upper shield structure and the lower shield structure have a series of grounded reference shields that reduce unwanted electrical signal interferences.

Abstract: A memory read response is received from a memory controller in response to a memory request and includes specific data and specific metadata attendant to the specific data retrieved with specific memory addresses in the device memory. The specific data and specific metadata are sent to a host device in a host-bound memory read response. In response to determining that a metadata update condition is satisfied, a number of actions are performed as follows. Specific modified metadata attendant to the specific data is determined. A MEMC-bound memory write request for metadata update is generated. The MEMC-bound memory write request is used to write the specific modified metadata attendant to the specific data in the device memory. The specific data and the specific modified metadata are stored in an entry of a temporary write buffer until the entry is invalidated by the corresponding metadata update write acknowledgement returned from the MEMC.

Abstract: An integrated circuit component receives a data block and corresponding error correction code from one or more external memory components in a memory read operation and then executes error detection/correction operations with respect to a plurality of input data volumes to generate a corresponding plurality of error syndrome values, the input data volumes each including the data block and corresponding error correction code together with a respective, different metadata bit patterns such that each of the input data volumes is identical to the others of the input data volumes except for the different metadata bit patterns. The integrated circuit component generates error qualification information by comparing error location information within the plurality of syndrome values with predetermined error location information and selects one of the metadata bit patterns to be an output metadata value based on the error syndrome values and the error qualification information.

Abstract: A chip-embedded logic analyzer autonomously sequences between logic analysis scenarios, dynamically revising match criteria and match-responsive behavior as match conditions for each successive scenario are met. Through this cascading-scenario operation, the logic analyzer may log selected debug vectors as and/or after complex sequences of device conditions unfold, enabling substantially more targeted and sophisticated operational debugging than conventional trigger-and-log analyzers.

Abstract: A total number V of virtual host-managed device memory (HDM) decoder configurations are generated for the same total number V of HDM memory regions attached to a non-host computing device. Each virtual HDM decoder configuration in the virtual HDM decoder configurations corresponds to a respective HDM memory region in the HDM memory regions. A proper subset of one or more virtual HDM decoder configurations is selected from among the virtual HDM decoder configurations to configure one or more physical HDM decoders of a total number P of the non-host computing device into one or more virtual HDM decoders. The one or more physical HDM decoders configured as one or more virtual HDM decoders are applied to translate a host physical address (HPA) received from a host computing device in a memory access transaction involving the host computing device and the non-host computing device.

Abstract: Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.

Abstract: Symbols are received, from a first computing device by a second computing device, across lanes of a communication link. A physical layer extracted HPA (or eHPA) is generated from the symbols while operations at a physical layer of a receiving (Rx) protocol stack of the second computing device are being performed. The eHPA is generated before other operations at other layers of the Rx protocol stack are finished. The eHPA is used to perform one or more operations for memory access before a normative message is formed by operations of the receiving protocol stack implemented in a communication interface of the second computing device.

Abstract: A signaling link retimer injects flow-rate compensation transmissions into a synthesized symbol stream in coordination with flow-rate compensation transmissions detected within a received symbol stream, enabling the retimer to switch seamlessly between forwarding the received symbol stream and outputting the synthesized symbol stream.

Abstract: A hot-swappable DRAM cartridge implemented in a standards-compliant SSD form-factor has an access panel that opens to enable removal and insertion of socketed DRAM memory modules. In at least some implementations, the DRAM cartridge complies with form-factor, protocol, connector, and pin-out/signal specifications set forth in one or more Enterprise and Data Center Standard Form Factor (EDSFF) specifications promulgated by Storage Networking Industry Association (SNIA) including, for example and without limitation, form-factor specifications set forth in EDSFF standards E3.S, E3.S 2T, E3.L and E3.L 2T.

Abstract: A motherboard implementing a T-topology bus architecture between a host controller and two or more DDR5 DIMM slots is combined with one or more DIMM terminator cards installed in at least one of the DDR5 DIMM slots to increase the performance of DDR5 DIMM memory accesses.

Abstract: An integrated-circuit retimer selectively logs information corresponding to mission-mode data, received and transmitted via counterpart high-bandwidth data interfaces, in real-time and accordance with contents of a logging control storage written by an external component during retimer run time.

Abstract: A memory control component encodes over-capacity data into an error correction code generated for and stored in association with an application data block, inferentially recovering the over-capacity data during application data block read-back by comparing error syndromes generated in detection/correction operations for respective combinations of each possible value of the over-capacity data and the read-back application data block.

Abstract: A decoding engine within an integrated-circuit (IC) component executes a first plurality of error detection/correction operations with respect to first and second pluralities of data volumes to generate a corresponding first and second pluralities of error syndrome values. Each data volume of the first plurality of data volumes includes a first data block and a first error correction code together with a respective one of a plurality of unique q-bit metadata values, and each data volume of the second plurality of data volumes includes a second data block and a second error correction code together with a respective one of the plurality of unique q-bit metadata values. Output circuitry within the decoding engine selects one of the plurality of q-bit metadata values to be an output q-bit metadata value according to error-count differentiation indicated by the first and second pluralities of error syndrome values.

Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Abstract: A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.

Abstract: A memory control component allocates a portion of an auxiliary signaling channel and corresponding memory storage, conventionally dedicated to error correction code (ECC) conveyance and storage, for conveyance of metadata and/or other types of component-level information—splitting the auxiliary channel between metadata and ECC conveyance/storage in proportions that obviate conventional metadata conveyance/storage via the primary data channel and thus maintaining full primary channel bandwidth/storage-capacity for user data.

Abstract: A memory control component encodes over-capacity data into an error correction code generated for and stored in association with an application data block, inferentially recovering the over-capacity data during application data block read-back by comparing error syndromes generated in detection/correction operations for respective combinations of each possible value of the over-capacity data and the read-back application data block.

Abstract: A total number V of virtual host-managed device memory (HDM) decoder configurations are generated for the same total number V of HDM memory regions attached to a non-host computing device. Each virtual HDM decoder configuration in the virtual HDM decoder configurations corresponds to a respective HDM memory region in the HDM memory regions. A proper subset of one or more virtual HDM decoder configurations is selected from among the virtual HDM decoder configurations to configure one or more physical HDM decoders of a total number P of the non-host computing device into one or more virtual HDM decoders. The one or more physical HDM decoders configured as one or more virtual HDM decoders are applied to translate a host physical address (HPA) received from a host computing device in a memory access transaction involving the host computing device and the non-host computing device.

Abstract: A decoding engine within an integrated-circuit (IC) component iteratively executes error detection/correction operations with respect to a sequence of input data volumes to generate a corresponding sequence of error syndrome values, the input data volumes each including a first block of data and corresponding error correction code retrieved from one or more external memory components together with a respective one of a plurality of q-bit data patterns. Selector circuitry within the decoding engine selects one of the plurality of q-bit data patterns to be an output q-bit value according to error-count differentiation indicated by the error syndrome values.

Abstract: A memory control device implements split storage of user-data and metadata components of a compound write data word, outputting the user-data component via a memory control interface for storage within an external memory subsystem while separately storing the metadata component within a metadata cache implemented within the memory control device.