Abstract: An adaptive time-discrete filter having an impulse response h(i) with i=0,1,2, . . . for forming a cancelling signal from synchronous data symbols (for example to cancel echoes or lagging intersymbol interference) comprises a transversal filter section (12) having adjustable coefficients C.sub.i with i=0,1,2, . . . , N-1 for realizing the first N values h(i) of the impulse response as well as a recursive filter section (12') for realizing the values h(i) with i=N,N+1, . . . . The recursive filter section (12') receives the input signal delayed over N-1 discrete time intervals from the adaptive filter as an input signal x(n) and forms an output signal y(n) according to the relationship:y(n)=C.sub.B [C.sub.A .times.(n-1)+y(n-1)]where C.sub.A is equal to the last adjustable coefficient C.sub.N-1 of the transversal filter section (12) and C.sub.B is a predetermined fixed coefficient.

Abstract: The connector comprises two conector portions (1, 3), each of which comprises an inner contact member (5, 49) which is coaxially surrounded by an outer contact member (23, 59) whereto it is mechanically connected via an insulating body (9, 53). At its free end each contact member (5, 23, 49, 59) comprises a contact face (5', 23', 49', 59') which extends perpendicularly to its axis, at least one (5', 59') of each pair of cooperating contact faces (5', 23'; 49', 59') being so large that, after the coupling of the two connector portions (1, 3), a suitable electrical connection is realized between the cooperating contact members (5, 23; 49, 59) it the axes of the two connector portions have been displaced with respect to one another no more than a predetermined distance (d).

Abstract: Decoding unit for CMI-encoded input signals. A signal having 0/1 transitions is first derived from a signal. A 0/1 transition occurs in a CMI-signal as the result of encoding a binary zero or two consecutive binary ones. In the latter case the 0/1 transition is preceded two bits earlier by a 1/0 transition. By deriving a signal having 1/0 transitions, delaying this signal by two bit intervals and by comparing it to the first signal, the 0/1 transitions corresponding to a binary zero are then accurately detected. The resultant signal can easily be extended by one bit period, so that independent of any phase inversions of the read clock, the appropriate binary information is always generated.

Abstract: A switching system for switching-through in time-division multiplex broadcast connections and point-to-point connections. In prior art broadcast switching systems the incoming (transmitter) channels are fed with multiplicity into the switching system and distributed there in accordance with a distribution algorithm. This multiple feed-in is effected in the switching system of the invention in a time-division multiplex switching stage divided into parallel units as a result of which the switching rate of this stage does not become excessively high. In order to realise this parallel distribution of this time-division switching stage a certain restriction of the distribution algorithm must be tolerated.It has been found that the switching system thus obtained is suitable for multislot connections, whilst it can also be rendered suitable for point-to-point connections by slightly extending it.

Abstract: Electronic gain control is achieved by means of a differential controller in combination with a multistage, feedback amplifier. Both the input impedance and the output impedance have a low ohmic value, so that the influence of parasitic capacitances in the differential controller on the bandwidth is significantly reduced.

Abstract: Adaptive filter for producing an echo cancellation signal in a transceiver system arranged for digital communication in the duplex mode via one single pair of conductors, the filter comprising delay means (8) having N terminals for delaying the N most recently transmitted symbols, an addressing circuit (10) having M input terminals (M<N), each of which is coupled to the terminals 1 to M of the delay means, the addressing circuit forming from the signals applied to the input terminals an address for a memory (11) in which for each of these addresses always a first correction signal is stored; a weighting and summing arrangement (9) having N input terminals coupled to the N terminals of the delay means, the arrangement providing a second correction signal which is a weighted sum of all the signals at the input terminals thereof, means (12) for adding together the first correction signal and the second correction signal and an adaptive control loop (13).

Abstract: The invention relates to a switching system for a broadband ISDN-network by means of which signals can be transmitted with a large variety of bit rates. In addition to 64 kbit/s, 144 kbit/s and 2 Mbit/s narrow-band channels for inter alia telephony, data, video-information broadband channels for, for example, broadcast-TV having bit rates from 35-70 Mbit/s are switched through. For both signal catagories, a common switching system of the TST-type is utilised, which avoids the necessity of providing a multiplexer for each subscriber. The control of the time switching stages and the space switching stage forming part of the switching system is divided in a control for the broadband channels and a control for the narrow-band channels. Thus, a simple, effective control of the switching system is realised which operates at a low rate whenever possible.

Abstract: An optical high-impedance preamplifier for processing signals over a large dynamic and automatically operating control range. The automatic control is provided by a variable impedance which is arranged in series with the source circuit of a current-stabilized input MOSFET of the optical preamplifier. As a result thereof, no overloading or loss of sensitivity occurs at a high or low input level.

Abstract: In the future ISDN network, up to eight subscriber terminals for speech, data and image traffic can be connected to the network terminating circuit (NT). The interface between the subscriber terminals and the network terminating circuit - the S-interface - is specified in CCITT Recommendation I.430. The transmitter in the S-interface must satisfy many, sometimes conflicting, requirements. This is satisfied to an optimum extent by providing the transmitter with a bridge circuit formed by semiconductor switching elements which are controlled by a digital control circuit. According to the invention, the output current of the transmitter is maintained substantially constant with the aid of a differential amplifier connected to the bridge circuit.

Abstract: The invention relates to a broadband space switching network and to a parallel-series converter and to a series-parallel converter in combination with such a space switching network. The crosspoints of the space switching network are set once per n-bit word. So as to find the time required therefor, each word contains (n-n.sub.1) "idle" bits, n.sub.1 representing the number of information bits. During the time in which the "idle" bits are transmitted, the space switching network is switched to the desired new state. The parallel-series converter, which is also required for other reasons, is used to inject "idle" bits into the bit stream conveyed to the space switching stage. The "idle" bits are removed again by means of a series-parallel converter at the output of the space switching stage.

Abstract: Adaptive transversal filter for use with three-signal level signals, arranged to cancel shifts in the two extreme signal levels relative to the central signal level, information signaling whether the signal level is the central signal level being coupled to first delay means (2) having N+1 connecting terminals, and information signaling whether the signal level is either one or the other extreme signal level being coupled to second delay means (4) having N+1 connecting terminals and comprising first and second coefficient registers (C.sub.OO -C.sub.ON ; C.sub.O -C.sub.sN) each containing N+1 coefficients; means (8, 9) for always multiplying one of the coefficients by an associated connecting terminal signal of the delay means, means (10) for adding together all the multiplying results obtained for providing a cancellation signal and means for always blocking the signal from a connecting terminal of the second delay means when this signal represents neither the one nor the other extreme signal level.

Abstract: In digital systems clock signals are generated from an external clock reference signal for the purpose of synchronization with the aid of a phase-control loop 1 incorporating a frequency-controllable oscillator 2. In practice synchronization problems occur due to the phase inaccuracy of these clock signals relative to the clock reference.By a two-level control of the oscillator frequency in a plurality of cycles, located within a period of the clock reference signal, using a pulse-width modulator 12, the phase accuracy of a clock signal to be derived from the oscillator output signal is improved.In a preferred embodiment the loop 1 comprises: storage means 16, control means 17 and selection means 18 for providing in accordance with a given phase control strategy a phase-accurate oscillator output signal, this accuracy already being obtained on a small time scale.