Abstract: A cache optimization method which analyzes an existing cache mapping scheme and determines a new cache mapping scheme that eliminates cache collisions. In a first embodiment, an application is traced while running in its main working set by a processor to obtain cache access statistics for objects within the working set under the first caching scheme. The cache access statistics are analyzed to obtain collision information which reveals lines of operating memory that collide in cache memory. Addresses are assigned to the objects using a cache-miss prediction algorithm. If the cache memory is too small to store all of the objects within the working set, the working set is divided into a plurality of working subsets which each contain a smaller number of objects than the working set. Finally, system calls are executed by the processor to effect the second cache mapping scheme.

Abstract: A scaling apparatus is disclosed for horizontally and vertically scaling scan line information stored in a video memory prior to providing the scan line information to a computer display. Horizontal scaling apparatus is provided in which a first clock signal is provided for graphics portions of scan lines and a second clock signal is provided for video portions of scan lines. The second clock signal is enabled in a manner such that the second clock signal exhibits a predetermined phase relationship with respect to the first clock signal from scan line to scan line. The frequency of the second clock signal is selected to determine the scaling of the video portion of the scan line. Vertical scaling apparatus is provided in which scan line information corresponding to first and second scan lines is retrieved from a video memory.

Abstract: An integrated circuit formed on a semiconductor substrate has a contact pad for communicating signals between an external device and an internal signal line. The pad is protected by an SCR that conducts electrostatic discharge pulses from the pad directly to a current sink. The SCR includes a subregion underneath a field oxide that has a field inplant that increases the dopant concentration. The field implant lowers the SCR trigger voltage, so that SCR triggers before an ESD pulse can cause latch-up or damage in other devices in the integrated circuit.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: A method and apparatus for operating parallel databases in a multi-processor computer system. Client Applications interact with a Navigation Server executing on the computer system, and through it, with one or more Data Servers. The Navigation Server receives requests from the Client Applications, which it compiles or translates into a plurality of parallel SQL statements. These parallel SQL statements are communicated to particular ones of the Data Servers for execution. The Data Servers, each of which may execute on different processors in the computer system, perform their respective SQL statements and thus access their database partitions concurrently and in parallel, thereby reducing the overall access time of a given request from a given Client Application. The computer system behaves, and is presented to users, as if the database resides under the control of a single Data Server, even though the database is partitioned across multiple Data Servers.

Abstract: The invention concerns a stylus for producing a high-voltage, sinusoidal signal for an electrostatic digitizing pad. The high voltage is obtained by applying a sine wave to one lead of the primary of a transformer, and applying the inverse of the sine wave to the other lead of the primary. The secondary of the transformer produces the high voltage, which is developed into a signal which is applied to the digitizing pad.

Abstract: The clock rate for a device is controlled through the use of integrated circuits which respond to the temperature of the device. Circuitry is added to the integrated circuit device being controlled which changes the clock rate of the device as the device temperature changes. The device clock is thus regulating by the temperature of the device. The way in which the regulation is implemented can be varied, from slowing an internally generated clock rate, or by digitally scaling an external clock input. Synchronous scaling is also provided, such that devices which are connected external to the CPU can still be clocked at the same external rate, but CPU transactions within the CPU may occur at a different rate depending on the CPU's measured temperature. This invention also provides the ability to selectively reduce or stop certain areas of an integrated circuit relative to pending operations or instructions being executed.

Abstract: A semiconductor structure comprising a polysilicon pad, a metal pad separated from the polysilicon pad by an insulator, and a metal via connecting the pads. A fuse is formed at the intersection of the polysilicon pad and via.

Abstract: A single-edge triggered phase detector which provides high speed phase detection. The phase detector works on only a single edge of the clock and data signal, which can be either the rising or falling edge. Extracted control signals are latched for at least one half of a clock period or more to ensure full rail to rail swing.

Abstract: A method and architecture for a graphics controller chip. The graphics controller has a display memory for storing video and graphics data. It also has a logic controller, connected to the memory, for performing logic operations on data stored in the memory. Video and graphics data is made available to the graphics controller at a single access port. The graphics controller also has an address range detector for checking the address of the data provided to the port and for disabling logical operations of the logic controller when the address indicates the presence of video data. The video data is thereafter transferred to the display memory on a priority basis.

Abstract: A method of planarizing a non-planar substrate, such as filling vias and contact holes, spreads a suspension of a conducting material suspended in a liquid on a substrate. The suspension includes an organometallic material, preferably with particles of a polymerized tin or indium alkoxide. The material is spread by spinning the substrate after applying the suspension. The carrier liquid and organic groups are removed by baking and curing at elevated temperatures, thereby depositing the conductive material on the substrate in a layer which is more planar than the substrate and which has regions of greater and lesser thickness. A relatively brief etch step removes conductive material from regions of lesser thickness, leaving material filling vias or contact holes.

Abstract: A data communication method and apparatus includes an integral bit error rate test system. The system is adapted to receive digital data signals to be transmitted over a communication link and includes a transmitter for transmitting the data signals onto the link. A test signal pattern generator generates a determinable pattern of digital bit test signals which are insertable into an input of the transmitter in place of the digital data signals. A receiver is coupled to the link for receiving the bit test signals and for comparing the received pattern of the bit test signals to the determinable pattern. The bit error rate is computed from the number of bit differences between the transmitted test signals and the determinable pattern.

Abstract: A SCSI-2-and-DMA processor that has on a single integrated circuit a SCSI-2 interface for a SCSI-2 data bus that is at least two bytes wide and a DMA interface for a system data bus that is at least two bytes wide. This integrated circuit has an set of control registers and an on-chip processor such that the transfers involving SCSI-2 data transfers involving data words that have a width of at least two bytes can be processed and completed without burdening the remainder of the system. Substantially all that is needed of the system processor is to down load a very compact control program and then transfers between this integrated circuit and system RAM. The on-chip processor allows chaining of random length blocks of contiguous address data by using a chain mode of transfer which also pairs up any odd residue with a portion of the first word of the next block in the chain using on-chip processing.

Abstract: A scan-based logic test apparatus is provided for use with an automated test equipment (ATE) digital tester which tests scan-based logic IC devices. The test apparatus is embodied in a test card which is pluggable into a bus slot within a computer. The computer includes a permanent memory for storing scan-based pattern data including serial input pattern data and expected serial output pattern data. The test card includes an I/O interface control which interfaces the test card to the computer to permit retrieval of the scan-based pattern data from the permanent memory and which interfaces the test card to the digital tester to permit the tester to supply control signals to the test card. The test card further includes an SRAM memory which is coupled to the I/O interface control. The SRAM memory stores the scan-based pattern data including serial input pattern data and expected serial output pattern data upon retrieval thereof from the permanent memory by the I/O interface control.

Abstract: The invention concerns an adaptive driver circuit which can source and sink current when powered by different power supply voltages. The invention maintains the output voltage substantially constant, for a given load, when the voltage of the power supply changes.

Abstract: A method and apparatus for pseudo aligned transfers to memory for processors, peripherals and memories. Alignment logic, typically coupled to a peripheral, receives a plurality of data bytes from a processor. The alignment logic uses a control header transferred with the data bytes to determine whether the data bytes require re-alignment. To effect re-alignment, the alignment logic combines, rotates, and masks the data bytes as indicated by the control header.

Abstract: A signal generator and method that is tolerable to supply voltage fluctuations and differentials. A current switch is driven that is independent of the supply voltage. By clamping the slewing voltage at the gate of a transistor driver, the difference between the clamped gate voltage and the threshold turn on voltage of the driver will be constant with respect to the supply voltage. This will cause the transition edges of the driver's output voltage to be constant with respect to the supply voltage. This technique minimizes variations in the output signal edge transitions as the supply voltage varies over various tolerance ranges. Because this technique increases the control of the transition edges in the output signal, it is possible to generate much slower edges and still maintain a consistent transition voltage shape with variations in the supply voltage and the symbol width.

Abstract: The invention concerns fabrication of oxide-filled isolation trenches in integrated circuits. The invention etches a network of trenches in the surface of a uniformly doped wafer which has experienced no substantial processing steps. Such a wafer will have little, if any, surface damage. Such a wafer will etch to the same depth everywhere, because two major factors which affect etching rate are (a) surface damage and (b) doping non-uniformity, and these factors are absent. The trenches are then filled with oxide. They define islands upon which devices (such as transistors) may now be fabricated.

Abstract: A high-frequency phase locked loop circuit effectively increases the maximum frequency associated with the CMOS technology. The circuit includes a first phase-locked loop sub-circuit having an input and an output, a second phase-locked loop sub-circuit having an input coupled to the input of the first phase-locked loop circuit and an output, and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop sub-circuits and an output. The first and second phase-locked loop may be arranged in parallel or in a master/slave relationship.

Abstract: A power interface adapter that provides device power connections in a universal burn-in board system. The power interface adapter is a low-cost printed circuit board which interfaces on a one-to-one basis with each burn-in board device socket, thus providing a complete power interface connection. The power interface adapter offers a significant improvement over the present universal burn-in board power connection methods by eliminating device power related manufacturing limitations presently placed on universal burn-in board designs.