Abstract: In the disclosed call transfer method and circuitry, audibly distinguishable ringing signals at a station set enable an answering party to determine whether a received call is either the original call or a previously answered call. Line status LEDs at each station set give specific visual indications to trace the progress of a call transfer.

Abstract: A new soldering technique is being employed whereby solder is formed into pads, each pad connected to the next pad by a solder link. The pads are formed on center spacings equal to the spaces between assembly board terminals and heated to the melting point of the solder whereupon surface tension of the solder collapses the interconnecting pad links thereby leaving the terminals electrically isolated. The solder pad assembly is made by an etching process.

Abstract: Resistive battery feed circuits are normally not used because of lack of power supply noise rejection and attendant crosstalk coupling. In this circuit the opamp and surrounding circuitry insure that power supply and ground noise do not couple into the tip and ring circuits as a metallic signal and improve crosstalk attenuation. In addition, the opamp is used to split the 48 volt supply.

Abstract: In a liquid crystal display device, column signals intended to be applied to the liquid crystal material in first and second regions of the device are carried by first and second sets of column conductors disposed adjacent to a first substrate within the first and second regions, respectively. A portion of each second set conductor passes through the first region, but the singals thereon are prevented from being applied to the display material in the first region by using the first set conductors to shield from the display material that portion of each second set conductor which passes through the first region. In particular, the portion of each second set conductor that passes through the first region is disposed behind (relative to the display material) a respective first set conductor and is narrower than that first set conductor.

Abstract: This telephone switching system is comprised of a plurality of time slot interchangers (TSIs) which exchange information on an interleaved basis. The TSI's write and read this information in their associated port data store memories using common buses on a time shared basis. The interleaving permits faster call processing since the data store operates faster than its associated TSI and can therefore respond to read/write requests from a number of TSI's. The interleaving also permits each TSI processor to serve only certain types of calls, wherein each TSI may be equipped with a specialized processor adapted to serve a unique type of call such as conference, nonconference, data, etc.

Abstract: A cable supporting clamp (10) for the orderly routing of flat electrical cables (28, 29, 30) at the interconnection side of electrical equipment frames. A pair of jaws each formed of a pair of arms (18-19; 20-21) extending from one side of a backplate (15) define slots (22, 23) adapted to receive the cable or cables. The cables are trapped in the slots by a pair of nubs (24-25; 26-27) at each jaw extending inwardly into the slots at the ends of the jaw arms (18-19; 20-21). Bracket means (31, 35) are provided at the other side of the backplate (15) for slidably mounting the clamp (10) on a frame cross-member (11).

Abstract: Small communication systems do not have a sufficiently large memory to store the vast amount of data required to determine the cost of interstate telephone calls using the conventional method. The disclosed telephone call cost establishing method and apparatus compresses the amount of data required by supplying a set of coordinates for a central point in each area code. The cost of an interstate call to any central office in an area code is then determined using the coordinates of the central point for that area code. Additionally, certain types of calls are priced using a predetermined price code stored in a variety of tables such as toll call allowed, frequently called numbers, personal line and facility tables.

Abstract: The subject parity circuit generates a single parity bit for a prescribed DATA SET. The DATA SET comprises n bytes which are simultaneously transmitted to the parity circuit over n data transmission leads. The n bytes are simultaneously combined bit by bit to determine whether an odd or even number of bits have been received. A cummulative sum is determined, and the single parity bit is generated with the receipt of the last n bits of the DATA SET.

Abstract: There is disclosed a cross-connect having a hinged rotating section panel which accepts multi-pair cables. The hinged section is mounted to a forward edge of a support section and the multi-pair cables are suspended between the two sections so that the cables remain in the same plane regardless of the position of the hinged section. The user cross connects between the cable pairs using the familiar modular plug and jack. The design of the cross-connect field is modular so that the cross-connect field can easily be added to as the system grows. The forward edge of the support panel slopes vertically to insure that the patch cords dress properly from top to bottom.

Abstract: The digital terminal keyboard dialing arrangement of this invention enables a user to originate data calls directly from any digital terminal keyboard without requiring the use of an associated telephone station set. In particular, the subject telephone switching system has a control signalling channel between the digital terminals and the system processor. This control signalling channel is used to convey the ASCII output from the digital terminal keyboard directly to the system processor on a call origination. Upon call completion, the ASCII output from the digital terminal keyboard is routed to the called party via the switching network.

Abstract: The disclosed arrangement of digital signal processor and echo cancellor is connectable to four wire transmission facilities on a per port basis for providing adaptive signal conditioning to reduce noise and improve level contrast among conferees of a digital conference connection. The digital signal processor applies an adaptive gain value to incoming speech signals for either increasing or decreasing the level of these signals to meet a predetermined threshold. A fixed gain adjustment is applied to incoming noise signals to reduce the level of these signals. The arrangement also provides a last-talker holdover mode in which the last gain adjustment applied to last-talker speech is applied to idle channel noise on that line.

Abstract: There is disclosed a multifrequency tone distribution arrangement for a communication system having a common time division multiplexed bus in which digital samples of tone frequencies are supplied from a central signal generating circuit to system port circuits via selected time slots. Each port circuit automatically accepts selected signals from the common bus for conferencing to produce multifrequency digit tones and service tones.

Abstract: The subject telephone switching provides for the redirection of established data calls to remotely located digital terminals and the reservation of these digital terminals at the time a data call is originated. In particular, a user can originate a data call from a telephone station set, reserve a selected digital terminal which may or may not be colocated with the telephone station set, and at some point in the call, transfer the established data call to the selected digital terminal by operating a data button on the calling telephone station set.

Abstract: An input bit sequence is encoded for transmission on a QAM carrier by dividing a scrambled version of the input sequence into groups of N consecutive bits. Each group is then subdivided into first and second subsets of r and r.sup.1 bits, where r+r.sup.1 =N. At least one of the bits in the first subset is applied to a finite state machine (such as a convolution encoder) which is arranged to expand the applied bits by at least one additional bit, in accordance with a prescribed logic arrangement. At least one bit in the second subset is processed similarly but independently, using a different finite state machine, or by time sharing a single finite state encoder. The expanded bit subsets, which include at least r+1 and r.sup.1 +1 bits, respectively, are then mapped into in-phase and quadrature symbols such that the minimum euclidean distance for an error event is larger than that obtained from an uncoded system.

Abstract: Protocol support and message buffering circuitry is used to transmit call status, control and terminal management information bidirectionally over associated conductor pairs as signalling messages between a system processor and a phone and/or terminal served by the system and connected to each conductor pair. This information is transmitted serially in a modified HDLC format as a one bit signalling field of a multiplexed data frame. At each transmitting end, the message information is converted from a parallel to a serial format, transmitted serially as the signalling bit of successive frames, and reconverted to parallel at the receiving end.Ports terminate the system end of the conductor pairs and are mounted four to the board. Each board contains circuitry, such as registers and the like, common to the signalling message protocol support and message buffering circuitry of all four ports.

Abstract: This data call transfer arrangement enables a calling party to originate a data call from a telephone station set and then transfer the data call to one of a number of predefined digital terminals. This is accomplished by operating the DATA button on the telephone station set corresponding to the selected digital terminal once the data call is established. This action causes the subject telephone switching system to replace the telephone station set on the call appearance with the selected digital terminal.

Abstract: The subject invention is a precision controlled frequency synthesizer which is capable of precisely adjusting the frequency of an output signal to maintain a desired frequency difference between an input and output signal regardless of the stability of the frequency of an input signal. The synthesizer comprises the basic elements of a phase locked loop (PLL) type circuit. The PLL circuit portion detects the actual frequency difference, a value A, between the input and output signals. A reference source provides a desired frequency difference, a value D, which represents the frequency difference between a stable input frequency and a desired output frequency. The difference between the frequency difference values A and D serves as the amount of adjustment to the frequency of the output signal. This adjustment represents the amount of compensation necessary to maintain a specified frequency relationship between the input and output signals.