Abstract: A novel circuit recovers a carrier signal from a 16 or 64 QAM double sideband suppressed carrier IF signal for use in synchronolus demodulation. A 70 MHz IF signal is fed to a power splitter for distributing the signals to a demodulator and to a quadrupler. The 280 MHz signal from the quadrupler is fed to a surface acoustic wave filter to extract the components of the double sideband suppressed carrier signal and the output therefrom is amplified prior to being divided by four to recover the 70 MHz signal. The 70 MHz signal is delivered to a phase frequency detector which provides an error signal during acquisition to deviate a VCO toward the received frequency and thus obtain very fast acquisition time. When the VCO is locked, the phase frequency detector is disconnected from the summing node of a PLL, and a correlated error polarity adaptive carrier recovery circuit operates the demodulator.