Abstract: An interactive game film includes, on a video disk, data arranged in clips representing video film segments, each clip having a lead-in segment, a body segment, a loop segment, and a lead-out segment. Each clip matches at least one other, so that when the clips are played in series, the splice is seamless. The clips are displayed by a driver in response to instructions from a game control program unique to a particular game. The game control program provides an interface, in the form of visible or audible subtitles containing keywords, between a player and the driver, whereby the player can, at decision points in the game, control which film clip is displayed next.

Abstract: A raster graphics color palette architecture for multiple display objects or sprites includes a first memory for storing pen index information for each display object. The pen index information for each display object includes pen index information corresponding to each pixel of that display object. A second memory stores indexing information for each display object. The indexing information maps the pen index information for the corresponding display object to pen numbers. A pen palette device includes a number of dynamically alterable registers, or "pens," containing RGB information for driving a multicolor raster display. In operation, pen index information representing the pixels of a display object is accessed from the first memory. This pen index information is mapped into pen numbers using the indexing information for the display object stored in the second memory. These pen numbers are then coupled to the pen palette to provide the RGB information for driving a multicolor raster display.

Abstract: A system (60) for predicting CPU addresses includes a CPU (34) connected by bus (62) to page mode address predicting circuit (64). The page mode address predicting circuit (64) is connected to memory arbitration circuits (66) by bus (68). The memory arbitration circuits (66) are connected to RAM (42) by address, data and control busses (44), (46) and (48). The CPU (34), page mode address predicting circuit (64) and the memory arbitration circuits 66 are contained in a microprocessor integrated circuit (32). The page mode predicting circuit 64 examines signals from the CPU (34) to be supplied to the data bus (46) at the time of a SYNC pulse. This operation results in examination of the first byte of a CPU instruction to determine how many of the following memory accesses will be able to be carried out in high speed mode.

Abstract: A multi-directional switch assembly, such as a joypad or joystick for an electronic game apparatus, including a printed circuit board, a resiliently deformable member having contact elements thereon and an input member mounted to deform the deformable member to effect closing of the switches. The input member is pivotally mounted by a post assembly, and the post assembly is supported by the game apparatus housing in a manner which is independent of the printed circuit board to substantially isolate the printed circuit board from thrust forces manually applied to the joypad input member.

Abstract: A method and circuit generate a dependent clock signal from a master clock signal with minimal skew of the dependent clock signal with respect to the master clock signal and inverting it to create a second master clock signal that is one hundred eighty degrees out of phase with the first master clock signal. The second master clock signal is used to drive a flip flop type circuit so that the flip flop circuit changes states when the first master clock signal is at a "zero" level and the second master clock signal is at a "one " level. The output of the flip flop circuit is enabled using the first master clock signal. Connected to the output of the tri-state driver is a repeater circuit of the type having an output that remains the same as the input until the input level is changed.

Abstract: An invertible, hand-held, electronic game apparatus having a manually engageable housing, a display screen mounting in the housing, an electronic circuit electrically connected to drive the display screen, and a control switch assembly mounted for manipulation by at least one hand of the player while holding the housing. The control switch assembly includes a joypad and fire buttons which are positioned on the housing to permit rotation or inverting of the housing and operation of the switches in a rotated position. Inversion of the housing and operation of the switches is possible when the images are vertically or horizontally oriented. In the preferred form, the control switch assembly includes a joypad on one side of the display screen and two pairs of functionally duplicate fire buttons symmetrically positioned about a central plane of the housing on an opposite side of the screen. The back of the housing is formed with protruding convex surfaces to facilitate gripping.

Abstract: A video computer system and methods are disclosed for displaying video graphics on a video display screen. The video computer system employs two alternative video graphics controllers. A first graphics controller is typically one that has been previously available to consumers and which also has a substantial library of graphics programs which are designed to be executed compatibly thereon. The second graphics controller is typically not compatible with the first graphics controller, and accordingly executes a second type of graphics programs which also may not be compatibly executed on the first controller. A select circuit and methods are disclosed which automatically determine the type of graphics program presented to the system, and correspondingly selects the compatible graphics controller to execute the program.