Patents Assigned to Ateeda LTD
  • Patent number: 9246503
    Abstract: A method for testing a DAC including controlling the DAC digitally to cause it to produce a known desired analog output, for example a fixed amplitude sine wave; determining the duration of fixed voltage segments of the actual output of the DAC and using the duration of the fixed voltage segments to assess or determine performance of the DAC.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: January 26, 2016
    Assignee: ATEEDA LTD.
    Inventors: David Hamilton, Tom Clayton, Gordon Sharp, Ian Stevenson
  • Patent number: 9106247
    Abstract: A histogram-based method for testing an electronic converter device, such as an analogue to digital converter, includes steps of defining at least one histogram hyperbin arranged to store hits for at least one subrange of output codes; applying an input test stimulus to an input of the device to test a subrange of output codes matched to the hyperbin; and accumulating the histogram. At least two hyperbins may be provided, each bin being arranged to store hits for at least one subrange of output codes, and the input test stimulus is applied to an input of the device to test a subrange of output codes matched to one of the hyperbins. Both hyperbins may be open while the histogram is being accumulated for any subrange of output codes. The method may further involve varying the input stimulus to test another subrange.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: August 11, 2015
    Assignee: ATEEDA LTD.
    Inventors: David Hamilton, Gordon Sharp
  • Publication number: 20140203954
    Abstract: A histogram-based method for testing an electronic converter device, such as an analogue to digital converter, includes steps of defining at least one histogram hyperbin arranged to store hits for at least one subrange of output codes; applying an input test stimulus to an input of the device to test a subrange of output codes matched to the hyperbin; and accumulating the histogram. At least two hyperbins may be provided, each bin being arranged to store hits for at least one subrange of output codes, and the input test stimulus is applied to an input of the device to test a subrange of output codes matched to one of the hyperbins. Both hyperbins may be open while the histogram is being accumulated for any subrange of output codes. The method may further involve varying the input stimulus to test another subrange.
    Type: Application
    Filed: February 6, 2014
    Publication date: July 24, 2014
    Applicant: ATEEDA LTD.
    Inventors: David Hamilton, Gordon Sharp
  • Patent number: 8682613
    Abstract: A histogram-based method for testing an electronic converter device, such as an analogue to digital converter, includes steps of defining at least one histogram hyperbin arranged to store hits for at least one subrange of output codes; applying an input test stimulus to an input of the device to test a subrange of output codes matched to the hyperbin; and accumulating the histogram. At least two hyperbins may be provided, each bin being arranged to store hits for at least one subrange of output codes, and the input test stimulus is applied to an input of the device to test a subrange of output codes matched to one of the hyperbins. Both hyperbins may be open while the histogram is being accumulated for any subrange of output codes. The method may further involve varying the input stimulus to test another subrange.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: March 25, 2014
    Assignee: Ateeda Ltd.
    Inventors: David Hamilton, Gordon Sharp
  • Publication number: 20100328121
    Abstract: A method for testing a circuit that generates an n-bit pulse density modulated output in response to an input signal or combination of input signals, for example the analogue section (12) of an analogue to digital converter (25) that has an n-bit pulse density modulated output stream, the method comprising inputting a test signal to the circuit, converting the pulse density modulated output to an analogue signal and checking the actual analogue output against an expected output, thereby to identify any faults.
    Type: Application
    Filed: March 11, 2009
    Publication date: December 30, 2010
    Applicant: Ateeda LTD
    Inventor: David Hamilton