Abstract: Methods of manufacturing an antenna are presented. The antenna is capable of being mounted on a printed circuit board. In accordance with the method, the design dimension of a unitary piece of material are selected according to an operating wavelength. The unitary piece of material is stamped out from a larger section of material according to the design dimensions to form an antenna. The unitary piece of material includes a circular area and a stem area. The circular area has a center and an outer region. The stem area has a first end and a second end. The first end is joined with the center. The unitary piece is bendable at the first end and the center.

Abstract: Current OFDM systems use a limited number of symbols and/or sub-channels to provide approximations for channel estimations and pilot tracking, i.e. phase estimations. For example, two training symbols in the preamble of a data packet are used to provide channel estimation. Four of the fifty-four sub-channels are reserved for providing phase estimation. However, noise and other imperfections can cause errors in both of these estimations, thereby degrading system performance. Advantageously, decision feedback mechanisms can be provided to significantly improve channel estimation and pilot tracking in OFDM systems. The decision feedback mechanisms can use data symbols in the data packet to improve channel estimation as well as data sub-channels to improve pilot tracking.

Abstract: An on-chip signal transforming device includes a substrate and a first conductive layer above the substrate, wherein the first conductive layer has a plurality of interleaved inductors. The device further includes a second conductive layer above the substrate, wherein the second conductive layer has at least one inductor.

Abstract: The present invention provides an apparatus and method for optimizing power in order to increase capacity. Rather than having any terminal device limited to a specific maximum data rate, instead the terminal device data rate is limited by the power being used, such that the data rate can vary according to the distance that the terminal device is from the intended receiver.

Abstract: A system for detecting and avoiding interference with radar signals in wireless network devices is described. The receiver circuit of the device receives incoming 5 GHz traffic. Such traffic could comprise both WLAN traffic as well as radar signals from radar systems. The incoming packets are treated as an input event, and are screened to be examined as radar pulses. Radar pulses are identified using the length of the detected event. The radar pulses are examined using frequency domain analysis, and the packet train is examined to find gaps between radar pulses. The periodic nature of the packet is determined using frequency domain and time domain analysis to calculate the period of the pulse train. Particular intervals within the pulse train are analyzed using threshold numbers of periodic pulses within the interval and threshold power levels for the pulses. The calculated period information is used to identify the radar source and screen non-radar traffic.

Abstract: A control interface, which includes both master and slave devices, can provide buffering of input data packets, thereby allowing configurations of the integrated circuit to be modified quickly and efficiently. Additionally, the control interface can be sized and configured to receive digital signals from any number of nodes on an integrated circuit, thereby facilitating the testing, lab characterization, and debugging of those nodes. Finally, the control interface can advatageously control the monitoring of analog components on the integrated circuit, thereby significantly reducing the number of pins for such monitoring. The control interface has particular relevance to highly integrated circuits that utilize analog and/or mixed signals.

Abstract: A channel select filter circuit is disclosed using a current-mode transconductance-capacitor (gm-C) architecture, which is tuned by digitally controlled capacitor arrays. The main filter includes at least one transconductor-capacitor (gm-C) filter and a transresistance amplifier. A replica transconductor-capacitor (gm-C) filter and a phase detector are used to establish any phase shift in an input signal, and a state machine adjusts capacitor arrays in the the replica transconductor-capacitor (gm-C) filter and the at least one transconductor-capacitor (gm-C) filter in order to set a cut-off frequency of the channel select filter.

Abstract: A communication system such as an OFDM or DMT system has nodes which are allowed to transmit continuously on one or just a few of the sysiem's frequency sub-channels, while the other nodes avoid putting any signal into those sub-channels. Simple low data rate nodes are allowed to use a small number of sub-channels while more complicated nodes use the remainder, and preferably functionality is provided to ensure that adjacent sub-channels are reliably spaced apart in frequency so that they do not bleed over into one another; to ensure that signals from all nodes arrive at the base station with well-aligned symbol transitions; and to ensure that signals from the various nodes arrive at the base station with similar power levels.

Abstract: Systems to provide and methods to design a printed lumped-distributed balun are presented. A lumped-distributed balun includes a single-ended port, a first differential port, a second differential port, a first phase shifter circuit, and a second phase shifter circuit. The first phase shifter circuit includes a first inductor and a first capacitor. The first inductor is coupled to the single-ended port and the first differential port. The first capacitor is coupled to the first differential port and is adapted to be coupled to ground potential. At least one of the first inductor and the first capacitor is implemented as a transmission line structure, such as microstrip. The second phase shifter circuit includes a second inductor and a second capacitor. The second inductor is coupled to the second differential port and is adapted to be coupled to ground potential. The second capacitor is coupled to the single-ended port and the second differential port.

Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.

Abstract: An integrated circuit inductor structure has a substrate disposed below an inductor. The structure also has plural conductive segments located between the substrate and the inductor. The conductive segments connect at substantially a point below the center of the inductor. An insulating layer lies between the inductor and the conductive segments.

Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.

Abstract: The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.

Abstract: Systems and methods for mounting an antenna on a printed circuit board are presented. In accordance with the method, an opening is formed through a printed circuit board (PCB). The PCB has a bottom side and a transmission feed on a top side. The PCB is configured to receive an antenna through the opening. An antenna is inserted into the opening on the top side of the PCB. The antenna makes electrical contact with the transmission feed. The antenna is secured to the PCB at the bottom side of the PCB.

Abstract: A current-steering charge pump circuit and method for switch timing that reduces the amount of switching transients on an output current pulse produced by the charge pump. The charge pump circuit is especially adapted to control a voltage-controlled oscillator (VCO) in a phase-locked loop circuit.

Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.

Abstract: A Viterbi decoding system interprets bits in received QAM constellations as many-valued parameters rather than binary valued parameters. It performs the Viterbi algorithm using these many-valued parameters to provide results superior to hard decision decoding. Rather than applying a hard 0-1 function to the QAM data, the system uses a non-stepped linear or curved transfer function to assign values to the bits. This results in performance superior to pure hard decision decoding and approaches that of soft decision decoding; moreover, it is applicable in many situations where soft decision decoding cannot be used.

Abstract: The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator.

Abstract: The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator.

Abstract: A radio-frequency (RF) integrated circuit is described. In one embodiment, the IC comprises multiple metal layers forming multiple transistors on a non-epitaxial substrate. The transistors are step and mirror symmetric. Also, the RF signal lines are on a top metal layer above all other metal layers and the power and ground planes are on a bottom metal layer below all other metal layers. The top and bottom metal layers are separated by a shield that extends beyond the RF signal lines by a distance that is at least the same distance that the shield is away from the RF lines. Low frequency signals are on signal lines below the top metal layer.