Abstract: A network, network device and method is disclosed. A network of network nodes is disclosed in which the network nodes securely transmit communication signals using one or more spatial parameters unique to the network nodes. A dad positioning device capable of operating as a node in a network of the present invention is also disclosed.

Abstract: Clock compensation for GPS receivers. A receiver in accordance with the present invention comprises a Radio Frequency (RF) portion, and a baseband portion, coupled to the RF portion, wherein the baseband portion comprises a crystal, an oscillator, coupled to the crystal, wherein the oscillator generates a clock signal based on a signal received from the crystal, a counter, coupled to the oscillator via the clock signal, a comparator, coupled to the counter, a controller, at least one logic gate, coupled to the comparator and the controller, and a combiner, coupled to the at least one logic gate, the controller, and the counter and producing an accurate clock signal therefrom.

Abstract: Clock compensation for GPS receivers. A receiver in accordance with the present invention comprises a Radio Frequency (RF) portion, and a baseband portion, coupled to the RF portion, wherein the baseband portion comprises a crystal, an oscillator, coupled to the crystal, wherein the oscillator generates a clock signal based on a signal received from the crystal, a counter, coupled to the oscillator via the clock signal, a comparator, coupled to the counter, a controller, at least one logic gate, coupled to the comparator and the controller, and a combiner, coupled to the at least one logic gate, the controller, and the counter and producing an accurate clock signal therefrom.

Abstract: A network, network device and method is disclosed. A network of network nodes is disclosed in which the network nodes securely transmit communication signals using one or more spatial parameters unique to the network nodes. A dad positioning device capable of operating as a node in a network of the present invention is also disclosed.

Abstract: A matched filter for implementing the correlation of an input signal and a reference signal. The matched filter comprises N parallel M-sample long shift registers for receiving an equal number of input signals at the sampling frequency of the input signal, wherein N?2, and then multiplexes one of the input signals and one of the reference signals at a time to calculation logic by applying alternately at least one combination of the input signals and the reference signals to the calculation logic. The calculation logic may then calculate the correlation time-dividedly for each combination of an input signal and a reference signal so that correlation results calculated from different signals appear at the output of the calculation means as a sequence.

Abstract: A GPS receiver with automatic mode-setting and power ramping circuitry is disclosed.

Abstract: A network, network device and method is disclosed. In one embodiment, a method includes transmitting communication signals from a first network node to a second network node, where the first and second network nodes comprise a network and each include a receiver portion and a transponder portion. The method further comprises receiving, by the first and second network nodes, position signals from a plurality of navigation beacons, and generating transmitter codes for the transponder portions using local code generators of the receiver portions.

Abstract: The present invention relates to a device for generating at least one code phase (Ce, Cp, Ci) the device comprising a shift register (702) comprising N outputs and to which a code sequence (Cin) to be phased is applied, and at least one logic branch (722, 723, 724) controlled by at least one combination control signal on the basis of which the logic branch combines the code phase from i outputs of the shift register (702). N is an integer greater than 2 and i is an integer between 2 and N. Said at least one logic branch preferably comprises i two-input selectors (901 to 909, 911 to 919, 921 to 929), to the first input of each of which is connected one input of the shift register (702) and to the second input is connected one combination control signal (ec0 to ec8, pc0 to pc8, lc0 to lc8), and an i-input combiner (910, 920, 930), to whose outputs are connected the outputs of said i selectors and from whose output said code phase is obtained.

Abstract: A tuned low-noise amplifier is disclosed. A device in accordance with the present invention comprises a first current source, a second current source, a comparator, coupled to the first current source and the second current source, for providing a control signal, and a third current source, receiving the control signal and coupled to the tuned low-noise amplifier, wherein a current in the third current source is proportional to a current in the first current source and the second current source, where values of the first current source, the second current source, and the third current source are based on a quasi-Proportional-To-Absolute-Temperature (PTAT) curve.

Abstract: A system and method for networking a plurality of nodes is disclosed. A network of data devices having data representations of connectivity, network node position, and/or position topologies is also disclosed, wherein the network may be self-configuring and the network nodes spatially addressable. In another embodiment, a unique form of signal acquisition assistance intrinsic in the signal structure may also be used. A data positioning device capable of operating as a node in a network of the present invention is also disclosed.

Abstract: A two-bit offset canceling A/D converter with improved common mode rejection and threshold sensitivity for use in GPS receivers. A device in accordance with the present invention comprises a level shifter, the level shifter receiving a positive signal and a negative signal, the level shifter shifting the positive signal and the negative signal such that a difference between the positive signal and the negative signal is larger than a threshold value, and a comparator, coupled to the level shifter, the comparator providing as outputs of the comparators a sign bit and two magnitude bits wherein the comparator comprises a plurality of switched capacitor amplifiers.