Abstract: A method and apparatus for processing interrupts in a computing system include processing for ordering a plurality of interrupts for at least one processor. Such interrupts include system event interrupts, external device interrupts, and may further include power management interrupts, interprocessor interrupts, and/or intraprocessor interrupts. Such processing continues by generating an interrupt enable/disable signal based on the current context of a corresponding processor such that when the processor is performing a particular task which should not be interrupted, an interrupt signal is prevented from being provided to the processor. The processing also includes generating masking information to provide enable/disable masking information regarding each of the plurality of interrupts. As such, the computing system may enable/disable on a per interrupt basis the processing of a given interrupt.

Abstract: A method and apparatus for managing cache memory is described. The invention improves the efficiency of cache usage by monitoring parameters of multiple caches, for example, empty space in each cache or the number of cache misses of each cache, and selectively assigns elements of data or results to a particular cache based on the monitored parameters. Embodiments of the invention can track absolute values of the monitored parameters or can track values of the monitored parameters of one cache relative to one or more other caches. Embodiments of the invention may be scaled to accommodate larger numbers of caches at a particular cache level and may be implemented among multiple cache levels.

Abstract: In accordance with an embodiment of the present invention a digital representation of a YCbCr video signal data stream is received that represents a video image or a series of video images. Received Y data values are linearly transformed and used to provide an RGB signal. The RGB signal is non-linearly adjusted to provide an adjusted RGB signal that enhances the viewed brightness of the data. In a specific embodiment, the non-linear adjusting adjusts the brightness of data near a mid-range of the video image more than other ranges of data.

Abstract: A method and apparatus for video compression that provides support for the inclusion of VBI data and copy protection data in an enhanced encoded video data stream is presented. A received video signal is separated such that a video data stream and a VBI data stream are produced. The video data stream is encoded to produce a compressed video data stream. The various types of VBI data that may be included in the VBI data stream are isolated, and one or more are selected for inclusion in the enhanced video data stream. The compressed video data stream is then combined with the one or more VBI data type streams to produce the enhanced video data stream. In other embodiments, copy protection information in the video signal is also detected and encoded such that it also can be included in the enhanced video data stream. The enhanced video data stream can be stored in memory or some other type of storage media for retrieval at a later time.

Abstract: A lighting effect computation block and method therefore is presented. The lighting effect computation block separates lighting effect calculations for video graphics primitives into a number of simpler calculations that are performed in parallel but accumulated in an order-dependent manner. Each of the individual calculations is managed by a separate thread controller, where lighting effect calculations for a vertex of a primitive may be performed using a single parent light thread controller and a number of sub-light thread controllers. Each thread controller manages a thread of operation codes related to determination of the lighting parameters for the particular vertex. The thread controllers submit operation codes to an arbitration module based on the expected latency and interdependency between the various operation codes. The arbitration module determines which operation code is executed during a particular cycle, and provides that operation code to a computation engine.

Abstract: A service chip for use with a computer. The chip includes a CPU interface, a transceiver interface, an adaptive echo cancellation filter, a monitor, and first and second data synthesizers. The CPU interface receives a transmit sample sequence from a modem sample generator executing on a central processor of the computer, and presents a receive sample sequence to a modem sample receiver executing on the central processor. The transceiver interface presents data to a line interface, which includes digital-to-analog and analog-to-digital converters for converting samples to/from analog signals for transmission on a telephone line. The filter adapts in response to an echo correlation between data transmitted over a transmit channel of the modem and data received on a receive channel of the transceiver interface. The monitor monitors the transmit sample sequence for a data starvation condition.

Abstract: A method and apparatus for allocation and control of memory bandwidth within a video graphics system is accomplished by first determining the memory bandwidth needs of each of the plurality of memory clients in the video graphics system. Based on this determination, a plurality of timers are configured, wherein each of the timers corresponds to one of the plurality of memory clients. The timers associated with the memory clients store two values. One value indicates the memory access interval for the corresponding client, which determines the spacing between memory access requests that can be issued by that particular client. The other value stored in the time is a memory access limit value, which determines the maximum length of a protected access to the memory by that particular client. A memory controller in the system receives requests from the plurality of clients and determines the priority of the different requests.

Abstract: A video graphics adapter is configured to provide both parallel and sequential color components to separate display monitors. When in a first state, the video graphics adapter provides individual color components to a video-output independent of each other color component, such that an entire frame of a red component will be provided to a video-out port for prior to, or subsequently after, an entire frame of the green component being provided to the video-out port. Each color component is provided to a common port. In response to a second configuration state, a traditional parallel red, green, blue (RGB) data port will be generated in order to provide data to a display device. In yet another configuration state, both the individual color components are provided at a common port, and the individual color components are provided in parallel to an RGB port.

Abstract: Multiple graphic images are generated simultaneously. An object or a polygon is received by a 3D graphics pipeline whereby a first stage of the pipeline performs a world transform on the modeling space of the object or polygon. An object culling is performed on the world space to eliminate objects not within view. Lighting is applied to the object as appropriate. Two view transforms are performed in parallel. Backface culling is applied to the resulting data. A single backface culling algorithm can be applied to both of the view transform scenes. A projection transformation is applied to those objects remaining following the backface culling. The first and second view transformed scenes are rendered in order to produce a first target image and a second target image respectively.

Abstract: A configurable vertex blending circuit that allows both morphing and skinning operations to be supported in dedicated hardware is presented. Such a configurable vertex blending circuit includes a matrix array that is used for storing the matrices associated with the various portions of the vertex blending operations. Vertex data that is received is stored in an input vertex buffer that includes multiple position buffers such that the multiple positions associated with morphing operations can be stored. Similarly, the single position typically associated with skinning operations can be stored in one of the position buffers. The input vertex buffer further stores blending weights associated with the various component operations that are included in the overall vertex blending operation. An arithmetic unit, which is configured and controlled by a transform controller, performs the calculations required for each of a plurality of component operations included in the overall vertex blending operation.

Abstract: A method and apparatus for simultaneously communicating data over a plurality of data links, such as a bus, determines initial logic levels of data to the output on each of the plurality of data links and changes the logic levels, such as inverting the data, of at least some of the data to produce logic level adjusted data in response to determining the initial logic level of the data to reduce switching transitions of simultaneously switched output data over the plurality of data links.

Abstract: A method and apparatus for displaying 3-D stereoscopic images is disclosed. A first stencil is used to filter a right eye image. A second stencil is used to filter a left eye image. Generally, the first and second stencil will have mutually exclusive active areas. The filtered left eye image and filtered right eye image are combined to form a single 3-D image having both images. The combined image is displayed on a conventional monitor, and viewed through the use of a pair or 3-D blue/red type lenses.

Abstract: A method and computer for executing the method. A CPU is programmed to execute first and second processes, the first process programmed to generate a second representation in a computer memory of information of the second process stored in the memory in a first representation. A main memory divided into pages for management by a virtual memory manager that uses a table stored in the memory.

Abstract: A device configuration method and apparatus initializes a device such as at least one graphics processor, by detecting whether the at least one graphics processor requires a dedicated address space. If the device requires a dedicated address space, boot up code, such as the system bios, maps the dedicated address space to another address space prior to running of an operating system. This is done based on, for example, using at least one subclass code bit in a class code register in configuration space memory as both a device function identifier and as control data to control mapping of the dedicated address space to another address space. The method and apparatus provides a type of universal method and apparatus for relocating or disabling, for example, VGA resources, through PCI registers or other suitable registers while maintaining legacy processing for graphics and video applications.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: A method and apparatus for dynamic issuing of memory access instructions. In particular, a specific data access request that is about to be sent to a memory, such as a frame buffer, is dynamically chosen based upon pending requests within a pipeline. It is possible to optimize video data requests by dynamically selecting a memory access request at the time the request is made to the memory. In particular, if it is recognized that the memory about to be accessed will no longer be needed by subsequent memory requests, the request can be changed from a normal access request to an access request with an auto-close option. By using an auto close option, the memory bank being accessed is closed after the access, without issuing a separate memory close instruction.

Abstract: A frame rate converter that receives segments having an input frame rate and provides the segments at a rate of N times the frame rate, where each segment is selected from a group consisting of a frame or field, including: a storage device which stores the segments, where the segments include a first, second, and third segments; and a display device coupled to receive the segments from the storage device and to provide the first, second, and third segments, where the display device provides the first segment and then provides the second segment following completion of providing the first segment where the second segment is previously available or otherwise again provides the first segment. The frame rate converter further includes a decoder device, where the third segment includes a field that includes a top line of an alternate frame and is encoded in 3:2 format and where the decoder device adjusts a time stamp of the third segment.

Abstract: An impedance compensation circuit and method for an input/output buffer provides dynamic impedance compensation by using programmable impedance arrays and a dynamically adjustable on-chip load. Accordingly, among other advantages, only a single off-chip or external calibrated impedance resistor is used and only a single test pad is necessary.

Abstract: A method and apparatus for interfacing a bus with a plurality of input/output (I/O) devices includes steps for handling transactions to and from the I/O devices. Transactions from the I/O devices includes processing that begins by receiving the transactions, where each transaction is received at a rate corresponding to the providing I/O device. The processing continues by identifying, for each transaction, a corresponding section of memory for temporarily storing the transaction. The particular section of memory is identified based on the type of transaction and/or the identity of the I/O device. The processing then continues by storing each transaction in the identified section of memory when the section has an available entry. When the bus is available and a transaction has been selected, the selected transaction is provided to the bus at the rate of the bus.

Abstract: A method and apparatus locks a plurality of display synchronization signals, such as horizontal synchronization signals and a vertical synchronization signals, from a plurality of display output devices, such as a plurality of graphics processors. The method and apparatus digitally adjusts a vertical synchronization signal associated with a first display output device, with respect to a vertical synchronization signal associated with a second graphic output device until a crossover is detected between the first and second vertical synchronization signals. This provides a type of coarse synchronization. In response to detection of the first crossover, the method and apparatus digitally adjusts a horizontal synchronization signal associated with the first display output device with respect to a horizontal synchronization signal associated with the second display device to align the synchronization signals. The adjustment of the horizontal synchronization signals provides a fine synchronization adjustment.