Patents Assigned to ATI Technologies
  • Publication number: 20190188822
    Abstract: Techniques for improving data transfer in a system having multiple accelerated processing devices (“APDs”) are described herein. In such a system, multiple APDs are coupled to a processor (e.g., a central processing unit (“CPU”)) via a general interconnect fabric and to each other via a high speed interconnect. The techniques herein increase the effective bandwidth for transfer of data between the CPU and the APD by transmitting data to both APDs through the portion of the interconnect fabric coupled to each respective APD. Then, one of the APDs transfers data to the other APD or to the processor via the high speed inter-APD interconnect. Although data transferred “indirectly” through the helper APD takes slightly more time to be transferred than a direct transfer, the total effective bandwidth to the target is increased due to the high-speed inter-APD interconnect.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 20, 2019
    Applicant: ATI Technologies ULC
    Inventors: Syed Arshad Rahman, Michael I. Hvizdos, Leonid Shamis
  • Patent number: 10324860
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: June 18, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Patent number: 10324732
    Abstract: Described is a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size and power, boot strapping, and power management. A multi-purpose field programmable non-volatile system power controller and ASSP initializing block may be embedded in a processor, such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), or other chipset. This controller and initializing block may be a configurable, while maintaining specialization, hardware block. This block may be implemented as a complex programmable logic device or as a simple cascaded programmable logic array block, such as being the equivalent of a few hundred logic gates, for example. Described also is a method of performing power sequencing and boot strapping for internal and external blocks on a chipset. The method includes powering a system power controller and initializing block and saving a power-up sequencing in a nonvolatile wake-up table.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: June 18, 2019
    Assignee: ATI TECHNOLOGIES ULC.
    Inventors: Behrooz Karimian-Kakolaki, Darlington C. Opara
  • Patent number: 10318340
    Abstract: In one form, a computer system includes a central processing unit, a memory controller coupled to the central processing unit and capable of accessing non-volatile random access memory (NVRAM), and an NVRAM-aware operating system. The NVRAM-aware operating system causes the central processing unit to selectively execute selected ones of a plurality of application programs, and is responsive to a predetermined operation to cause the central processing unit to execute a memory persistence procedure using the memory controller to access the NVRAM.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: June 11, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Sergey Blagodurov, Gabriel H. Loh, Mauricio Breternitz
  • Patent number: 10319063
    Abstract: In a processing system including a plurality of graphics processing units (GPUs), the GPUs transfer compressed graphics streams composed of blocks of graphics data to one another. Some blocks of a compressed graphics stream, or parts thereof, may contain both compressed graphics data and meaningless data (referred to as data structure padding, or padding) that is used to align the graphics data, and some blocks may contain only padding. Before transferring a compressed graphics resource from one GPU to another GPU, the sending GPU compacts the compressed graphics resource by filtering out padding from the compressed graphics stream prepared for the transfer.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: June 11, 2019
    Assignee: ATI Technologies ULC
    Inventor: Guennadi Riguer
  • Publication number: 20190174140
    Abstract: A texture decompression method is described. The method comprises receiving a compressed texture block, determining a partition of pixels used for the compressed texture block, wherein the partition includes one or more disjoint subsets into which data in the compressed texture block is to be unpacked, unpacking data for each subset based on the determined partition, and decompressing each of the one or more disjoint subsets to form an approximation of an original texture block.
    Type: Application
    Filed: January 25, 2019
    Publication date: June 6, 2019
    Applicant: ATI Technologies ULC
    Inventors: Konstantine Iourcha, Andrew S. C. Pomianowski
  • Patent number: 10311236
    Abstract: Systems, apparatuses, and methods for performing secure system memory training are disclosed. In one embodiment, a system includes a boot media, a security processor with a first memory, a system memory, and one or more main processors coupled to the system memory. The security processor is configured to retrieve first data from the boot media and store and authenticate the first data in the first memory. The first data includes a first set of instructions which are executable to retrieve, from the boot media, a configuration block with system memory training parameters. The security processor also executes a second set of instructions to initialize and train the system memory using the training parameters. After training the system memory, the security processor retrieves, authenticates, and stores boot code in the system memory and releases the one or more main processors from reset to execute the boot code.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: June 4, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Kathirkamanathan Nadarajah, Oswin Housty, Sergey Blotsky, Tan Peng, Hary Devapriyan Mahesan
  • Patent number: 10310266
    Abstract: Described is a method and system to efficiently compress and stream texture-space rendered content that enables low latency wireless virtual reality applications. In particular, camera motion, object motion/deformation, and shading information are decoupled and each type of information is then compressed as needed and streamed separately, while taking into account its tolerance to delays.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: June 4, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Khaled Mammou, Layla A. Mah
  • Patent number: 10310985
    Abstract: Systems, apparatuses, and methods for accessing and managing memories are disclosed herein. In one embodiment, a system includes at least first and second processors and first and second memories. The first processor maintains a request log with entries identifying requests that have been made to pages stored in the second memory. The first processor generates an indication for the second processor to process the request log when the number of entries in the request log reaches a programmable threshold. The second processor dynamically adjusts the programmable threshold based on one or more first conditions. The second processor also processes the request log responsive to detecting the indication. Additionally, the second processor determines whether to migrate pages from the second memory to the first memory based on one or more second conditions.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 4, 2019
    Assignee: ATI Technologies ULC
    Inventors: Dhirendra Partap Singh Rana, Conrad Lai, Jeffrey G. Cheng
  • Patent number: 10304506
    Abstract: Systems, apparatuses, and methods for implementing dynamic clock control to increase stutter efficiency in a memory subsystem are disclosed. A system includes at least a processor, a memory, and a communication fabric coupled to the processor and memory. The system implements a stutter mode for a first region of the fabric, with stutter mode including an idle state and an active state. Stutter efficiency is defined as the idle time divided by the sum of the active time and the idle time. Reducing the exit latency of going from the idle state to the active state increases the stutter efficiency which increases the power savings achieved by implementing the stutter mode. Since the phase-locked loop (PLL) is one of the main contributors to the exit latency, the PLL is powered down and one or more bypass clocks are provided during the stutter mode.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: May 28, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Alexander J. Branover, Benjamin Tsien, Bradley Kent, Joyce C. Wong
  • Patent number: 10304155
    Abstract: Systems, apparatuses, and methods for compressing pixel data are disclosed. In one embodiment, if a block of pixel data is equal to a constant value, a processor compresses the block down to a metadata value which specifies the constant value for the entire block of pixel data. The processor also detects if the constant value is equal to a video specific typical minimum or maximum value. In another embodiment, the processor receives a plurality of M-bit pixel components which are most significant bit aligned in N-bit containers. Next, the processor shifts the M-bit pixel components down into least significant bit locations of the N-bit containers. Then, the processor converts the N-bit containers into M-bit containers. Next, the processor compresses the M-bit containers to create a compressed block of pixel data which is then stored in a memory subsystem.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: May 28, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Chan, Christopher J. Brennan
  • Publication number: 20190148345
    Abstract: In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.
    Type: Application
    Filed: January 14, 2019
    Publication date: May 16, 2019
    Applicant: ATI Technologies ULC
    Inventor: Changyok Park
  • Patent number: 10291931
    Abstract: Techniques are provided for determining variance of a pixel block in a frame of video based on variance of pixel blocks in a reference frame of the video, instead of directly, for example, by calculating variance based on pixel values of the pixel block. The techniques include identifying a motion vector for a pixel block in a current frame, the motion vector pointing to a pixel block in a reference frame. The techniques also include determining the cost associated with the motion vector and comparing the cost to first and second thresholds. The techniques include determining the variance for the pixel block of the current frame based on the comparison of the cost to the first and second threshold and based on the variance of the pixel block of the reference frame.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 14, 2019
    Assignee: ATI TECHNOLOGIES ULC
    Inventor: Mehdi Saeedi
  • Publication number: 20190122417
    Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.
    Type: Application
    Filed: November 2, 2018
    Publication date: April 25, 2019
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
  • Patent number: 10268620
    Abstract: Described herein are apparatus for connecting a first memory architecture locally to a graphics processing unit (GPU) through a local switch, where the first memory architecture can be a non-volatile memory (NVM) or other similarly used memories, for example, along with associated controllers. The apparatus includes the GPU(s) or discrete GPU(s) (dGPU(s)) (collectively GPU(s)), second memory architectures associated with the GPU(s), the local switch, first memory architecture(s), first memory architecture controllers or first memory architecture connector(s). In an implementation, the local switch is part of the GPU. The apparatus can also include a controller for distributing a large transaction among multiple first memory architectures. In an implementation, the first memory architectures can be directly connected to the GPU. In an implementation, the apparatus is user configurable. In an implementation, the apparatus is a solid state graphics (SSG) card.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 23, 2019
    Assignee: ATI Technologies ULC
    Inventor: Nima Osqueizadeh
  • Patent number: 10250909
    Abstract: A processing device for use with a video conferencing network is provided. The processing device includes memory configured to store data and a processor. The processor is configured to determine a first sampling phase for a portion of first video data and chrominance sub-sample the portion of first video data using the first sampling phase. The processor is also configured to encode the sub-sampled portion of first video data and decode a sub-sampled, encoded portion of second video data. The processor is further configured to determine a second sampling phase at which the portion of second video data is chrominance sub-sampled and chrominance up-sample the portion of second video data using the second sample phase.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 2, 2019
    Assignee: ATI Technologies ULC
    Inventors: Boris Ivanovic, Allen J. Porter
  • Patent number: 10241925
    Abstract: Systems, apparatuses, and methods for selecting default page sizes in a variable page size translation lookaside buffer (TLB) are disclosed. In one embodiment, a system includes at least one processor, a memory subsystem, and a first TLB. The first TLB is configured to allocate a first entry for a first request responsive to detecting a miss for the first request in the first TLB. Prior to determining a page size targeted by the first request, the first TLB specifies, in the first entry, that the first request targets a page of a first page size. Responsive to determining that the first request actually targets a second page size, the first TLB reissues the first request with an indication that the first request targets the second page size. On the reissue, the first TLB allocates a second entry and specifies the second page size for the first request.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: March 26, 2019
    Assignee: ATI Technologies ULC
    Inventors: Jimshed Mirza, Anthony Chan, Edwin Chi Yeung Pang
  • Patent number: 10242647
    Abstract: A data segmenter is configured to determine indices using numbers of most significant bits (MSBs) of fractional values of floating-point representations of component values of an input color that are selected based on exponent values of the floating-point representations. The component values are defined according to a source gamut. The data segmenter is also configured to determine offsets associated with the indices using subsets of the fractional values. An interpolator configured to map the input color to an output color defined according to a destination gamut based on a location in a three-dimensional (3-D) look up table (LUT) indicated by the indices and offsets.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 26, 2019
    Assignee: ATI Technologies ULC
    Inventor: Yuxin Chen
  • Patent number: 10243727
    Abstract: The present disclosure presents methods, apparatuses, and systems to bolster communication security, and more particularly to utilize a constant time cryptographic co-processor engine for such communication security. For example, the disclosure includes a method for secure communication, comprising receiving encrypted data at a receiving device; obtaining a randomization for at least one bit of the encrypted data; modifying an execution of a cryptographic algorithm on the at least one bit to obtain a randomized cryptographic algorithm based on the randomization; and executing the randomized cryptographic algorithm on the at least one bit of encrypted data to recover original data associated with the encrypted data.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: March 26, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Winthrop Wu, James Goodman, Martin Kiernicki, Yoichi Shimokawa, William Thomas Morrison, Creighton Eldridge, David Kaplan
  • Patent number: 10230370
    Abstract: In one form, a data transmission system includes transmission and reception circuits. The transmission circuit includes a first driver having an input for receiving a first transmit data signal, an output, a positive power supply terminal for receiving an input/output (I/O) power supply voltage, and a negative terminal for receiving an I/O ground voltage, a second driver having an input for receiving the I/O power supply voltage, an output, and a positive power supply terminal for receiving the I/O power supply voltage, and a third driver having an input for receiving the I/O ground voltage, an output, and a negative power supply terminal coupled to the I/O ground voltage. The reception circuit forms a reference voltage based an average of signal content below a predetermined frequency of outputs of the second and third drivers, and receives a signal from the output of the first driver using the reference voltage.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 12, 2019
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Fei Guo, Mark Edward Frankovich