Abstract: A host processing system assigns unequal time slices at a parallel processor to virtual functions based on profiles of applications executing at the virtual functions and an available budget of the parallel processor. The host processing system calculates a world switch cycle interval and assesses an available processing budget of the parallel processor. The available budget indicates the amount of graphics processing time the parallel processor has not yet allocated to virtual functions for each world switch cycle interval.

Abstract: Methods and devices are provided for processing data using a neural network. Activations from a previous layer of the neural network are received by a layer of the neural network. Weighted values, to be applied to values of elements of the activations, are determined based on a spatial correlation of the elements and a task error output by the layer. The weighted values are applied to the values of the elements and a combined error is determined based on the task error and the spatial correlation.

Abstract: An apparatus includes a storage location that is accessible to control plane circuitry and first circuitry configured to receive an interrupt indicating a fatal error. The first circuitry is also configured to provide, in response to the interrupt, first information indicating the fatal error to a data plane entity and second information indicating the fatal error to the storage location. The second information in the storage location is accessible via a control plane connection independently of the data plane entity initiating one or more recovery actions in response to receiving the first information. A system management controller (SMC) or a baseboard management controller (BMC) can be configured to access the second information in the storage location and convey the second information to control plane circuitry in a data center.

Abstract: Systems and methods for aligning flits including an apparatus or device including a first circuit corresponding to a data link layer, and a second circuit corresponding to a physical layer, the second circuit including a first sublayer, a second sublayer located between the first sublayer and an interconnect link, and an interface communicatively coupling the first sublayer to the second sublayer for transmission of code blocks between the first and second sublayers during data communications between the link partners, the code blocks align a first datagrams of the first sublayer to a second datagrams of the second sublayer based on alignment markers of the second datagrams. In a transmit direction, the first sublayer sends first code blocks to the second sublayer to indicate when to overwrite the alignment markers. In a receive direction, the second sublayer sends second code blocks to indicate when the first datagrams include alignment markers.

Abstract: Systems and methods for reducing, by a link partner, backlog at a receiver buffer of the other link partner. Each link partner includes at least one circuit coupled between a data fabric and an interconnect link of an interconnect fabric. The at least one circuit includes a receiver configured to receive datagrams from the interconnect fabric and a transmitter configured to send datagrams over the interconnect fabric. The transmitter is configured to monitor a loop latency for datagrams communicated between the link partners over the interconnect fabric using toggling handshake codes in their headers. Based on the monitored loop latency for the datagrams, the transmitter of a link partner is configured to reduce a receiver buffer backlog at the other link partner. The loop latency monitoring can include monitoring an unloaded and loaded loop latencies and comparing a difference between the loop latencies to one or more thresholds.

Abstract: Systems and devices for packing one or more sequence numbers into datagrams for transmission to a link partner over an interconnect fabric, the link partners including a transmitter in communication with a receiver for data transmission over the interconnect link, each of the transmitter and the receiver including at least one circuit. The at least one circuit packages a header and a data payload into data packets for transmission to the other of the transmitter and the receiver. Responsive to a request from the transmitter or the receiver, the at least one circuit of the transmitter or the receiver encodes a first sequence number and a second sequence number into the header of the data packet for transmission to the other of the transmitter or the receiver. The first sequence number may be a transmitter sequence number, and the second sequence number may be a receiver sequence number.

Abstract: Systems and devices for Universal Asynchronous Receiver Transmitter (UART) mode communication may include a first circuit including a first receiver transmitter in communication with a second receiver transmitter of a second circuit over an interconnect link. In a transmit direction, the first circuit is configured to pack stream transport data into data flits of a datagram for serialized transmission of data from the first receiver transmitter to the second receiver transmitter over the interconnect link. In a receive direction, the first circuit is configured to unpack the stream transport data from the data flits received as serialized data over the interconnect link from the second circuit of the second receiver transmitter. The stream transport data can be firmware data packed into the data flits as data link messages, which may be exchanged between firmware agents associated with the respective first circuit and second circuit.

Abstract: Systems and devices for packaging first data flits into second data flits may include at least one circuit of a first processor. In a transmit direction, the at least one circuit receives first data flits and packages the data of the first data flits into second data flits for transmission to at least one second processor over an interconnect link. In a receive direction, the at least one circuit receives a second data flit and packages the data into one or more first data flits for transmission to the first processor. The first data flit and second data flit may be a transaction layer flit and data layer flit, respectively. The second data flit may include a flit header, a cyclic redundancy check, and a plurality of segments, each segment including a segment header, an integer number of sectors, and one or more portions for storing the first data flits.

Abstract: An apparatus and method for efficiently managing performance among replicated modules of an integrated circuit despite manufacturing variations across semiconductor dies. An integrated circuit includes a first module with a first partition of multiple dies that share at least a same first power rail. The integrated circuit also includes a second module with a second partition of multiple dies that share at least a same second power rail different from the first power rail. The dies within partitions have differences in circuit parameters within a threshold such that the dies can be placed in a same first bin. The dies in different partitions belong to different bins. A power manager initially assigns the same operating parameters to the first partition and the second partition, but adjusts the operating parameters based on detection of the different circuit behavior due to manufacturing variations between the first partition and the second partition.

Abstract: An electronic device that includes a decompression engine that includes N decoders and a decompressor decompresses compressed input data that includes N streams of data. Upon receiving a command to decompress compressed input data, the decompression engine causes each of the N decoders to decode a respective one of the N streams from the compressed input data separately and substantially in parallel with others of the N decoders. Each decoder outputs a stream of decoded data of a respective type for generating commands associated with a compression standard for decompressing the compressed input data. The decompressor next generates, from the streams of decoded data output by the N decoders, commands for decompressing the data using the compression standard to recreate the original data. The decompressor next executes the commands to recreate the original data and stores the original data in a memory or provides the original data to another entity.

Abstract: A quantum dot liquid crystal display has a backlight generated by a light emitting diode (“LED”) that is typically blue and a quantum dot film that performs color conversion to red and green to produce white light. While cheap and efficient, the LEDs in such displays illuminate the pixels unevenly, and the distribution of uneven illumination is different for different wavelengths of light (e.g., red, green, and blue). A technique to compensate for this aspect includes measuring certain optical characteristics of the uneven illumination distribution, processing such measurements, and applying the results of such processing to the “desired” input image to generate an output image for display.

Abstract: An efficient confidential compute check is described. In one or more implementations, an apparatus includes a plurality of processors each configured to execute memory translations of at least one client that map client virtual memory to corresponding allocations of a physical memory shared among the plurality of processors. The apparatus also includes a security circuit configured to authorize client access to allocated regions of the physical memory based on whether an intercepted memory translation corresponds to an authorized client.

Abstract: A voltage regulator assembly can include a power stage chip and an inductive component coupled to the power stage chip. A footprint of the power stage chip can be bonded to a surface of a printed circuit board. The inductive component can include at least one coil, wherein a first portion of the coil is disposed on or over a surface of the power stage chip. The printed circuit board, the power stage chip, and the first portion of the coil can be arranged in a stack. The voltage regulator assembly can be configured to provide one or more power supply signals via the inductive component.

Abstract: Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical inference application are disclosed. A system includes a safety-critical inference application, a safety monitor, and an inference accelerator engine. The safety monitor receives an input image, test data, and a neural network specification from the safety-critical inference application. The safety monitor generates a modified image by adding additional objects outside of the input image. The safety monitor provides the modified image and neural network specification to the inference accelerator engine which processes the modified image and provides outputs to the safety monitor. The safety monitor determines the likelihood of erroneous processing of the original input image by comparing the outputs for the additional objects with a known good result. The safety monitor complements the overall fault coverage of the inference accelerator engine and covers faults only observable at the network level.

Abstract: Mutable firmware commonality for hardware root of trust is described. In at least one aspect, a system includes a volatile memory circuit having a first region that persistently stores a reusable portion of instructions executed during a boot sequence for establishing a hardware root of trust among multiple security layers of a security framework, and a second region that is overwritten during the boot sequence with each layer-specific portion of the instructions executed sequentially to implement a corresponding security layer based on the reusable portion. The system further includes a processing circuit that sequentially establish the hardware root of trust one security layer at a time by loading the second region of the volatile memory with a current layer-specific portion of the instructions that are executed in combination with the reusable portion of the instructions to implement a current security layer.

Abstract: Techniques for implementing programmable control by a guest virtual machine (VM) of interrupts at a processing system using a guest owned backing page are disclosed. The VM programs a guest owned backing page (e.g., a data structure in memory) that designates particular interrupts that are to be blocked. In response to detecting a designated interrupt, system hardware or software blocks the interrupt, rather than executing an interrupt handler to process the interrupt. The VM is thereby able to protect confidential information and program behavior with less risk of a malicious hypervisor failing to protect the VM from, e.g., unexpected or unwanted interrupts, thereby improving overall system security and predictability.

Abstract: A processor includes a security processor and an input-output memory management unit (IOMMU). The security processor is configured to maintain device control information in a secure data structure and prevent a hypervisor from accessing the secure data structure. The IOMMU is configured to process at least one device request targeting a virtual machine from an input/output device based on the secure data structure.

Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated memories that use separate power domains. Data of a given type is stored in an interleaved manner among the multiple memories. When control circuitry detects an idle state, commands are sent to the multiple memories specifying storing data of the given type in a contiguous manner in the memories connected to multiple functional blocks. Subsequently, the control circuitry transitions all but one of the memories to the sleep state. The memories rotate amongst themselves with a single memory being in the active state and servicing requests based on which data of the given type is targeted by the requests.

Abstract: A system utilizes a hybrid chroma subsampling process in which a source device generates a plurality of motion layers from an input image of a video stream. Each motion layer is associated with a different motion criterium and includes data from the image only for those regions of pixels that meet the corresponding motion criterium. The source device generates each motion layer with a different degree of chroma subsampling based on the motion criterium associated with the motion layer. The resulting plurality of motion layers are transmitted to a sink device. The sink device decodes the motion layers and then generates a composite image from the resulting motion layers, the composite image representing the input image with different degrees of chroma subsampling for different regions based on the degree of motion in each region.

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.