Patents Assigned to ATI Technologies ULC
  • Publication number: 20240121192
    Abstract: The disclosed device for packet coalescing includes detecting a trigger condition for initiating packet coalescing of packet traffic and sending, to an endpoint device, a notification to start packet coalescing. The device can observe a status in response to starting the packet coalescing and report a performance of the packet coalescing. A system can include a controller that detects a trigger condition for packet coalescing and notifies an endpoint device via a notification register. The controller can read a status register to report, based on the read status, a packet coalescing performance. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: March 31, 2023
    Publication date: April 11, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ashwini Chandrashekhara Holla, Indrani Paul, Alexander J. Branover, Carlos Javier Moreira
  • Patent number: 11954792
    Abstract: Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: April 9, 2024
    Assignee: ATI Technologies ULC
    Inventors: Benjamin Koon Pan Chan, William Lloyd Atkinson, Clarence Ip, Tung Chuen Kwong
  • Patent number: 11954782
    Abstract: A method, system, and non-transitory computer readable storage medium for rasterizing primitives are disclosed. The method, system, and non-transitory computer readable storage medium includes: generating a primitive batch from a sequence of one or more primitives, wherein the primitive batch includes primitives sorted into one or more row groups based on which row of a plurality of rows each primitive intersects; and processing each row group, the processing for each row group including: identifying one or more primitive column intercepts for each of the one or more primitives in the row group, wherein each combination of primitive column intercept and row identifies a bin; and rasterizing the one or more primitives that intersect the bin.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: April 9, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio
  • Patent number: 11953965
    Abstract: Techniques are described for adaptive device power management. The device interface application of a hardware computing unit detects a launch of an application by the operating system (OS) to be executed on the hardware computing unit, in an implementation. The device interface application identifies the launched application and determines whether a hardware profile exists that is associated with the application. The hardware profile includes one or more hardware parameters that yield the optimal performance for power consumption by the hardware computing unit when executing the launched application. Based on determining that the hardware profile exists, the power policy of the OS is updated for the launched application, and thereby, the driver updates the power state(s) of the hardware computing unit based on the new power policy.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: April 9, 2024
    Assignee: ATI Technologies ULC
    Inventors: Mohammad Hamed Mousazadeh, Joohyun Lee, Omer Irshad, Xuetao Yan, Alexander Sabino Duenas, Muhammad Saad Musani
  • Patent number: 11956441
    Abstract: Methods and devices are provided for encoding a video stream which comprise encoding a plurality of frames of video acquired from different points of view, generating statistical values for the frames of video determined from values of pixels of the frames, generating, for each of the plurality of frames, a perceptual hash value based on statistical values of the frame and encoding a current frame comprising video acquired from a corresponding one of the different points of view using a previously encoded reference frame based on a similarity of perceptual hashes of the current frame and the previously encoded reference frame.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: April 9, 2024
    Assignee: ATI Technologies ULC
    Inventors: Sunil Gopal Koteyar, Sonu Thomas, Ihab M. A. Amer, Haibo Liu
  • Patent number: 11955982
    Abstract: An apparatus and method for efficiently generating clock signals. An integrated circuit includes multiple clock dividers both at its I/O boundaries and across its semiconductor die. A clock divider receives an input clock signal, and an indication of a reduction factor that is a positive, non-zero and a non-integer value less than one. The clock divider generates an output clock signal based on the input clock signal and the reduction factor. The reduction factor can be an M-bit pattern where M is a positive, non-zero integer greater than one. Therefore, the clock divider generates the output clock signal with a reduced clock rate that has a smallest configurable granularity that is 1/M of the input clock frequency. An asserted bit in the M-bit pattern indicates that the output clock signal should have an asserted value during a corresponding clock cycle of the input clock signal.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: April 9, 2024
    Assignee: ATI Technologies ULC
    Inventor: Erwin Chi Wang Pang
  • Publication number: 20240112392
    Abstract: Devices and methods for node traversal for ray tracing are provided, which comprise casting a first ray in a space comprising objects represented by geometric shapes, traversing, for the first ray, at least one first node of an accelerated hierarchy structure representing an approximate volume of a group of the geometric shapes and a second node representing a volume of one of the geometric shapes, casting a second ray in the space, selecting, for the second ray, a starting node of traversal based on locations of intersection of the first ray and the second ray and an identifier which identifies one or more nodes intersected by the first ray and traversing, for the second ray, the accelerated hierarchy structure beginning at the starting node of traversal.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: David William John Pankratz, Konstantin I. Shkurko
  • Publication number: 20240111688
    Abstract: A technique for servicing a memory request is disclosed. The technique includes obtaining permissions associated with a source and a destination specified by the memory request, obtaining a first set of address translations for the memory request, and executing operations for a first request, using the first set of address translations.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Omar Fakhri Ahmed, Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Jason Todd Arbaugh, Milind Baburao Kamble, Philip Ng, Xiaojian Liu
  • Publication number: 20240113875
    Abstract: A method and apparatus for storing keys in a key storage block includes processing a key request. A first key is allocated based upon the key request. The first key is stored in the key storage block, wherein the first key is of a first size and includes a first rule.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed, Hemaprabhu Jayanna, John Traver
  • Publication number: 20240111620
    Abstract: The disclosed computer-implemented method for generating remedy recommendations for power and performance issues within semiconductor software and hardware. For example, the disclosed systems and methods can apply a rule-based model to telemetry data to generate rule-based root-cause outputs as well as telemetry-based unknown outputs. The disclosed systems and methods can further apply a root-cause machine learning model to the telemetry-based unknown outputs to analyze deep and complex failure patterns with the telemetry-based unknown outputs to ultimately generate one or more root-cause remedy recommendations that are specific to the identified failure and the client computing device that is experiencing that failure.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Mohammad Hamed Mousazadeh, Arpit Patel, Gabor Sines, Omer Irshad, Phillippe John Louis Yu, Zongjie Yan, Ian Charles Colbert
  • Publication number: 20240112297
    Abstract: Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to determine, for an input tile of an image, a receptive field via backward propagation and determine a size of the input tile based on the receptive field and an amount of local memory allocated to store data for the input tile. The processor determines whether the amount of local memory allocated to store the data of the input tile and padded data for the receptive field.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Tung Chuen Kwong, Ying Liu, Akila Subramaniam
  • Patent number: 11947473
    Abstract: Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: April 2, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Haikun Dong, Kostantinos Danny Christidis, Ling-Ling Wang, MinHua Wu, Gaojian Cong, Rui Wang
  • Patent number: 11948073
    Abstract: Systems, apparatuses, and methods for adaptively mapping a machine learning model to a multi-core inference accelerator engine are disclosed. A computing system includes a multi-core inference accelerator engine with multiple inference cores coupled to a memory subsystem. The system also includes a control unit which determines how to adaptively map a machine learning model to the multi-core inference accelerator engine. In one implementation, the control unit selects a mapping scheme which minimizes the memory bandwidth utilization of the multi-core inference accelerator engine. In one implementation, this mapping scheme involves having one inference core of the multi-core inference accelerator engine fetch given data and broadcast the given data to other inference cores of the inference accelerator engine. Each inference core fetches second data unique to the respective inference core.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 2, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Lei Zhang, Sateesh Lagudu, Allen Rush
  • Patent number: 11948534
    Abstract: A display system modifies display cycles of one or more displays to perform a system operation while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods of the one or more displays such that blanking periods equal or exceed a blackout duration and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: April 2, 2024
    Assignee: ATI Technologies ULC
    Inventors: Jun Lei, Syed Athar Hussain, David I. J. Glen, Rajeevan Panchacharamoorthy, Fatemeh Amirnavaei, David Galiffi, Arshad Rahman, Boris Ivanovic
  • Publication number: 20240104844
    Abstract: Devices and methods for multi-resolution geometric representation for ray tracing are described which include casting a ray in a space comprising objects represented by geometric shapes and approximating a volume of the geometric shapes using an accelerated hierarchy structure. The accelerated hierarchy structure comprises first nodes each representing a volume of one of the geometric shapes in the space and second nodes each representing an approximate volume of a group of the geometric shapes. When the ray is determined to intersect a bounding box of a second node representing one group of the geometric shapes, a selection is made between traversal and non-traversal of other second nodes based on a LOD for representing the volume of the one group of geometric shapes.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Sho Ikeda, Paritosh Vijay Kulkarni, Takahiro Harada
  • Publication number: 20240106438
    Abstract: An integrated circuit includes a power supply monitor, a clock generator, and a divider. The power supply monitor is operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage. The clock generator is operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency control word. The divider is responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Kaushik Mazumdar, Ashish Jain, Joyce Cheuk Wai Wong, Mikhail Rodionov
  • Publication number: 20240103591
    Abstract: Power management using temperature gradient information is described. In accordance with the described techniques, temperature measurements of a component are obtained from two or more sensors of the component. A temperature of a hotspot of the component is predicted based on the temperature measurements obtained from the two or more sensors of the component. Operation of the component is adjusted based on the predicted temperature of the hotspot.
    Type: Application
    Filed: December 29, 2022
    Publication date: March 28, 2024
    Applicant: ATI Technologies ULC
    Inventors: Adam Neil Calder Clark, Anil Harwani, Amitabh Mehra
  • Publication number: 20240106813
    Abstract: A method and system for distributing keys in a key distribution system includes receiving a connection for communication from a first component. A determination is made whether the first component requires a key be generated and distributed. Based upon a security mode for the communication, the key generated and distributed to the first component.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed, Hemaprabhu Jayanna, John Traver
  • Publication number: 20240103897
    Abstract: Systems and methods are disclosed for managing diversified virtual memory by an engine. Techniques disclosed include receiving one or more request messages, each request message including a job descriptor that specifies an operation to be performed on a respective virtual memory space, processing the job descriptors by generating one or more commands for transmission to one or more virtual memory managers, and transmitting the one or more commands to the one or more virtual memory managers (VMMs) for processing.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 28, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed
  • Patent number: 11942405
    Abstract: A semiconductor package assembly includes a semiconductor package that includes a semiconductor chip bonded to a substrate. The assembly also includes a plurality of passive devices mounted on a bottom surface of the substrate opposite the semiconductor chip, the plurality of passive devices including a plurality of operable passive devices and a plurality of standoff passive devices, wherein a height of each of the plurality of standoff passive devices is greater than a height of any of the plurality of operable passive devices. The assembly also includes a plurality of solder structures attached to the bottom surface of the substrate. When mounted on a circuit board, the standoff passive devices prevent solder bridging.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: March 26, 2024
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Jianguo Li, Roden Topacio