Patents Assigned to ATI Technologies ULC
  • Patent number: 11930168
    Abstract: An encoder calculates a first local encoding parameter for a first block of video content based on one or more local metrics. The encoder modifies the first local encoding parameter based on one or more second local encoding parameters for one or more second blocks of video content that are adjacent to the first block of video content. The encoder then encodes the first block using the modified first local encoding parameter. In some cases, the local encoding parameters are quantization parameters used to quantize values of pixels or compression parameters used to compress values of the pixels. The local metric can include one or more of a target bit rate, a texture complexity, a contrast, an indicator of motion in the first block, and an importance map.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 12, 2024
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Mehdi Saeedi, Boris Ivanovic
  • Patent number: 11915359
    Abstract: Systems, apparatuses, and methods for implementing kernel software driven color remapping of rendered primary surfaces are disclosed. A system includes at least a general processor, a graphics processor, and a memory. The general processor executes a user-mode application, a user-mode driver, and a kernel-mode driver. A primary surface is rendered on the graphics processor on behalf of the user-mode application. The primary surface is stored in memory locations allocated for the primary surface by the user-mode driver and the kernel-mode driver is notified when the primary surface is ready to be displayed. Rather than displaying the primary surface, the kernel-mode driver causes the pixels of the primary surface to be remapped on the graphics processor using a selected lookup table (LUT) so as to generate a remapped surface which stored in memory locations allocated for the remapped surface by the user-mode driver. Then, the remapped surface is displayed.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: February 27, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Jason Wen-Tse Wu, Parimalkumar Patel, Jia Hui Li, Chao Zhan
  • Patent number: 11908065
    Abstract: A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: February 20, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Daniel James Skinner, Michael John Livesley, David William John Pankratz
  • Patent number: 11899520
    Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: February 13, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ashish Jain, Benjamin Tsien, Chintan S. Patel, Vydhyanathan Kalyanasundharam, Shang Yang
  • Patent number: 11902532
    Abstract: Systems, apparatuses, and methods for performing machine learning content categorization leveraging video encoding pre-processing are disclosed. A system includes at least a motion vector unit and a machine learning (ML) engine. The motion vector unit pre-processes a frame to determine if there is temporal locality with previous frames. If the objects of the scene have not changed by a threshold amount, then the ML engine does not process the frame, saving computational resources that would typically be used. Otherwise, if there is a change of scene or other significant changes, then the ML engine is activated to process the frame. The ML engine can then generate a QP map and/or perform content categorization analysis on this frame and a subset of the other frames of the video sequence.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: February 13, 2024
    Assignee: ATI Technologies ULC
    Inventors: Sunil Gopal Koteyar, Mingkai Shao
  • Patent number: 11886367
    Abstract: An arbitration system receives requests to access a destination during an arbitration window that spans multiple processor clock cycles. During each clock cycle, the destination is monitored to determine whether the destination is suffering from backpressure by receiving more requests than the destination is able to accommodate during the clock cycle. In response to detecting backpressure, a masking index value assigned to a requesting source is incremented, which limits an amount of requests from the source that will be granted destination access during a subsequent arbitration window. Alternatively, in response to detecting an absence of backpressure during an arbitration window, the masking index value is decremented, which increases the amount of requests from the source that will be granted destination access during a subsequent arbitration window.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: January 30, 2024
    Assignee: ATI Technologies ULC
    Inventors: Michael E. McLean, Philip Ng
  • Patent number: 11886878
    Abstract: An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: January 30, 2024
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Sukesh Shenoy, Adam N. C. Clark, Indrani Paul
  • Patent number: 11880926
    Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: January 23, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
  • Patent number: 11868225
    Abstract: An electronic device includes a memory and a processor. The processor receives a platform management profile that includes information defining one or more platform management policies, a given platform management policy among the one or more platform management policies including a provided input from a specified hardware or software sensor and/or a provided output action. The processor uses the given platform management policy for controlling operating states of elements in the electronic device.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 9, 2024
    Assignee: ATI Technologies ULC
    Inventors: Alexander Sabino Duenas, Ashwini Chandrashekhara Holla, I-Cheng Chen, Xinzhe Li
  • Publication number: 20240004583
    Abstract: A random-access memory (RAM) includes a plurality of memory banks, a memory channel interface circuit, and a metadata processing circuit. The memory channel interface circuit couples to a memory channel adapted for coupling to a memory controller. The metadata processing circuit is connected to the memory channel interface circuit and receiving a poison bit sent over the memory channel associated with a write command and write data for the write command. The RAM, responsive to the poison bit indicating that the write data is poisoned, stores at least one of: the poison bit and a code indicating a value of the poison bit in a selected memory bank.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Aaron John Nygren, Michael John Litt
  • Publication number: 20240004453
    Abstract: Methods and systems are disclosed for managing the power consumed by cores of a system on chip (SoC). Techniques disclosed include obtaining application information that is indicative of an application being executed on the cores, detecting a workload associated with the application, and limiting one or more operating frequencies of the cores responsive to the detection of the workload. Techniques disclosed also include profiling the detected workload and limiting the one or more operating frequencies of the cores based on the profiling.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ashwini Chandrashekhara Holla, Alexander S. Duenas, Xinzhe Li, Indrani Paul, Karthik Rao
  • Publication number: 20240004444
    Abstract: Methods and systems are disclosed for managing performance states of a data fabric of a system on chip (SoC). Techniques disclosed include determining a performance state of the data fabric based on data fabric bandwidth utilizations of respective components of the SoC. A metric, characteristic of a workload centric to cores of the SoC, is derived from hardware counters, and, based on the metric, it is determined whether to alter the performance state.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Karthik Rao, Indrani Paul, Dana Glenn Lewis, Brett Danier Anil Ramautarsingh, Jeffrey Ka-Chun Lui, Prasanthy Loganaathan, Jun Huang, Ho Hin Lau, Zhidong Xu
  • Patent number: 11860797
    Abstract: Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: January 2, 2024
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Philip Ng, Nippon Raval, David A. Kaplan, Donald P. Matthews, Jr.
  • Patent number: 11862066
    Abstract: A graphics processing unit (GPU) instructs a display control module to capture content and display captured content in response to the refresh rate of a display exceeding a frame generation rate of the GPU. Rather than re-transmit the same frame multiple times, the GPU instructs the display control module to replay a previously-transmitted frame. During a refresh cycle in which the display control module is replaying captured content, the GPU omits accessing memory to retrieve and resend the frame that is being replayed, and instead sends only invalid data and GPU timing information so that the display control module remains synchronized with the GPU.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: January 2, 2024
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Anthony W L Koo, Syed Athar Hussain
  • Patent number: 11861781
    Abstract: The graphics processing unit (GPU) of a processing system transitions to a low-power state between frame rendering operations according to an inter-frame power off process, where GPU state information is stored on retention hardware. The retention hardware can include retention random access memory (RAM) or retention flip-flops. The retention hardware is operable in an active mode and a retention mode, where read/write operations are enabled at the retention hardware in the active mode and disabled in the retention mode, but data stored on the retention hardware is still retained in the retention mode. The retention hardware is placed in the retention state between frame rendering operations. The GPU transitions from its low-power state to its active state upon receiving an indication that a new frame is ready to be rendered and is restored using the GPU state information stored at the retention hardware.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 2, 2024
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Sreekanth Godey, Ashkan Hosseinzadeh Namin, Seunghun Jin, Teik-Chung Tan
  • Patent number: 11857877
    Abstract: An approach is provided for a gaming overlay application to provide automatic in-game subtitles and/or closed captions for video game applications. The overlay application accesses an audio stream and a video stream generated by an executing game application. The overlay application processes the audio stream through a text conversion engine to generate at least one subtitle. The overlay application determines a display position to associate with the at least one subtitle. The overlay application generates a subtitle overlay comprising the at least one subtitle located at the associated display position. The overlay application causes a portion of the video stream to be displayed with the subtitle overlay.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 2, 2024
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Wei Liang, Ilia Blank, Patrick Fok, Le Zhang, Michael Schmit
  • Patent number: 11863769
    Abstract: A system configured to perform scalable video encoding is provided. The system includes a memory; and a processing unit, wherein the processing unit is configured to: receive inter-layer data and a current picture, wherein the current picture has a base layer; upsample the inter-layer data to generate residual data and reconstruction data, wherein the inter-layer data includes a base mode flag; and encode the current picture to an enhanced layer using the upsampled inter-layer data based on a block type of the base layer and the base mode flag.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: January 2, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Lei Zhang, Ji Zhou, Zhen Chen, Min Yu
  • Publication number: 20230421173
    Abstract: Huffman packing for delta compression is described. In accordance with the described techniques, delta values between neighboring elements of a data block are generated using delta compression. The delta values are transformed according to a transformation algorithm. The transformed delta values are packed using Huffman encoding to generate compressed data that corresponds to the data block.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Applicant: ATI Technologies ULC
    Inventors: Yaser ElSayed, Angel Serah, Jing Xie
  • Publication number: 20230421787
    Abstract: A technique for encoding video is provided. The technique includes for a first portion of a first frame that is encoded by a first encoder in parallel with a second portion of the first frame that is encoded by a second encoder, determining a historical complexity distribution; determining a first bit budget for the first portion of the first frame based on the historical complexity distribution; and encoding the first portion of the first frame by the first encoder, based on the first bit budget.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Applicant: ATI Technologies ULC
    Inventors: Wei Gao, Gabor Sines, Ihab M. A. Amer, Crystal Yeong-Pian Sau, Feng Pan, Dong Liu
  • Publication number: 20230420018
    Abstract: A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Xuan Chen, Chih-Hua Hsu, Pradeep Jayaraman, Abdussalam Aburwein