Abstract: The disclosed device includes an input/output (I/O) system clock configured to operate at one of a plurality of clock states and a control circuit configured to dynamically adjust a clock state of the I/O system clock. The control circuit can update an activity level of a current clock state based at least on I/O traffic activity and, in response to the activity level going beyond an activity range for the current clock state, transition the I/O system clock to a neighboring clock state. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed device includes a device comprising a device-attached memory and a trust controller for confidential computing. The trust controller can maintain a record of devices that are permitted to access the device-attached memory, receive updates to the record, and verify, based on the record, attempts to access the memory.

Abstract: A computing device and a method of performing crash analysis is provided. Each compute unit of an accelerated processor is configured to execute an application in a crash analysis operation mode, different from a normal operation mode, by executing a single instruction in isolation from any other instruction such that execution of the single instruction is completed prior to beginning execution of any of the other instructions. Examples of selectable crash analysis operation modes include a first mode in which execution of each memory instruction is completed prior to beginning execution of a next instruction, a second mode in which execution of each ALU instruction is completed prior to beginning execution of a next instruction, and a third mode in which execution of both memory and ALU instructions are completed prior to beginning execution of a next instruction.

Abstract: An integrated circuit device performs a method for adjusting a clock signal frequency. The method includes receiving a workload, and determining a latency parameter by sampling data of the workload. Further, an activation parameter is determined based on a data bandwidth on the workload. A clock signal of the IC device is adjusted based on the latency parameter and the activation parameter.

Abstract: A request is received from an application to present content generated by the application in an overlay plane of a multi-plane display system. Responsive to determining that current system resources support presentation of the generated content in the overlay plane, frames of the generated content are displayed in the overlay plane and captured directly from the overlay plane such that the captured frames may be provided to one or more remote client computing systems independently of frames captured from one or more additional overlay planes and from an underlying composited desktop layer. Identifiers of prioritized applications may be maintained based on user preferences to determine specific applications for which generated content is enabled for display via overlay plane.

Abstract: An electronic device includes a package substrate having a top surface and a bottom surface. An integrated circuit (“IC”) die is disposed on the top surface of the package substrate. The electronic device also includes a stiffener having a ring body and a plurality of support members. The ring body is secured to the top surface of the package substrate and circumscribes the IC die. The plurality of support members extend from the ring body to below the bottom surface of the package substrate.

Abstract: An apparatus and method for efficiently creating less computationally intensive nodes for a neural network. In various implementations, a computing system includes a memory that stores multiple input data values for training a neural network, and a processor. Rather than determine a bit width P of an integer accumulator of a node of the neural network based on bit widths of the input data values and corresponding weight values, the processor selects the bit width P during training. The processor adjusts the magnitudes of the weight values during iterative stages of training the node such that an L1 norm value of the weight values of the node does not exceed a corresponding weight magnitude limit.

Abstract: Apparatuses, systems and methods for routing requests and responses targeting a shared resource. A queue in a communication fabric is located in a path between the requesters and a shared resource. In some embodiments, the shared resource is a shared address translation cache stored in an endpoint. The physical channel between the queue and the shared resource supports multiple virtual channels. The queue assigns at least one entry to each virtual channel of a group of virtual channels where the group includes a virtual channel for each address translation request type from a single requester of the multiple requesters. When the at least one entry for a given requester is de-allocated, the queue allocates this entry only with requests from the assigned virtual channel even if the empty entry is the only available entry of the queue.

Abstract: A technique for performing ray tracing operations is provided. The technique includes, in a first iteration of a ray traversal technique, traversing to an instance node of a bounding volume hierarchy; in a second iteration of the ray traversal technique that is subsequent to the first iteration, transforming a ray based on an instance transform of the instance node to generate a transformed ray; and in the second iteration, performing a ray-box intersection test for box node data of the instance node based on the transformed ray.

Abstract: A processor configured to execute one or more virtual machines (VMs) includes an input-output memory management unit (IOMMU) configured to handle memory-mapped input-output (MMIO) requests and direct memory access (DMA) requests from a processor core of the processor or one or more input/output (I/O) devices. In response to receiving an MMIO or DMA request, the IOMMU is configured to determine a VM associated with the request. The IOMMU then checks a security indicator field of an address space identifier (ASID) mask table to determine if the VM was previously the target of an attack by a malicious entity. In response to the VM previously being a target of an attack, the IOMMU denies the received MMIO or DMA request.

Abstract: Multiple guard rows are included in a region of memory. Accesses to the region of memory are monitored and a revolver technique using the guard rows is enabled in response to the number of accesses to the region of memory equaling or exceeding a threshold amount within a given interval of time. The guard rows are moved around the region of memory with one or more non-guard rows being situated between the guard rows. A guard row refers to a row of the region of memory that stores invalid data, whereas the one or more non-guard rows store valid data. After being moved, accesses to the region of memory are monitored and after another threshold number of accesses to the region of memory the guard rows are moved again. This process continues with the guard rows being moved, e.g., in a circular manner, through the region of memory.

Abstract: Systems, methods, and non-transitory computer-readable media for dynamic voltage margin adjustment are disclosed. In some aspects, a system includes a processor, a power supply monitor (PSM) configured to measure voltage levels of the processor, and a voltage control module. The voltage control module may monitor minimum voltage levels reported by the PSM, compare the minimum voltage levels to one or more thresholds, and dynamically adjust a voltage margin applied to the processor based on the comparison. The voltage margin adjustment may be performed in real-time and may account for different workload characteristics, potentially optimizing processor performance and power efficiency.

Abstract: Allocating peripheral component interface express (PCIe) streams in a configurable multiport PCIe controller, including: detecting, by a PCIe controller, a link by a first PCIe device; and allocating, for the link between the PCIe controller and the first PCIe device, a first one or more PCIe streams from a pool of PCIe streams.

Abstract: A technique for performing ray tracing operations is provided. The technique includes for a ray being tested for intersection with geometry associated with a bounding volume hierarchy, traversing to a pre-filtering node that includes information for filtering out triangles of a leaf node of the bounding volume hierarchy; evaluating a quantized ray that corresponds to the ray against quantized triangles of the pre-filtering node to filter out one or more triangles of the leaf node from consideration; and testing the triangles of the leaf node that are not filtered out and not testing the triangles of the leaf node that are filtered out.

Abstract: Systems, apparatuses, and methods for implementing memory bandwidth reduction techniques for low power convolutional neural network inference applications are disclosed. A system includes at least a processing unit and an external memory coupled to the processing unit. The system detects a request to perform a convolution operation on input data from a plurality of channels. Responsive to detecting the request, the system partitions the input data from the plurality of channels into 3D blocks so as to minimize the external memory bandwidth utilization for the convolution operation being performed. Next, the system loads a selected 3D block from external memory into internal memory and then generates convolution output data for the selected 3D block for one or more features. Then, for each feature, the system adds convolution output data together across channels prior to writing the convolution output data to the external memory.

Abstract: Dynamically modifying voltage regulator modes based on a computing system workload is described. System management circuitry assesses activity and energy demands of a computing system’s hardware components for a given workload and adapts voltage regulator configuration settings to ensure that the voltage regulator is operating in a mode that is optimized for the workload. In some implementations, modifying voltage regulator configuration settings causes a voltage regulator to transition from a current mode to a different mode. Alternatively or additionally, modifying configuration settings causes the voltage regulator to continue operating in a current mode with a different rate of voltage mitigation.

Abstract: A technique for generating backward optical flow data includes identifying a forward velocity value of a picture element at first coordinates in a subsequent frame buffer that stores forward velocity values for a subsequent frame. The technique identifies second coordinates in a previous frame buffer that stores backward velocity values of a previous frame by adjusting the first coordinates based on a negated version of the forward velocity value. A backward velocity value for the picture element at the second coordinates in the previous frame buffer is set to the negated version of the forward velocity value of the picture element at the first coordinates in the subsequent frame buffer. An image is rendered in accordance with the backward velocity value for the picture element at the second coordinates in the previous frame buffer.

Abstract: Data for nodes of a bounding volume hierarchy can be represented in fixed-point format for compression. For good precision, fixed-point bounds are stored along with each node, where these bounds represent the minimum and maximum representable numbers in the format. While this provides good compression, there are ways in which this technique can produce undesirable results. For example, if the size of many or most of the bounding volumes in the fixed-point number space is significantly smaller than the bounds, then the representation of such bounding volume in the fixed-point space may be unnecessarily large, resulting in a large number of false positive intersections during BVH traversal. Thus, techniques are provided herein for setting certain bounding volumes as “always hit” in order to eliminate the bounding volumes from inclusion in the fixed-point bounds. This shrinks the fixed-point bounds, giving better precision for smaller bounding volumes.

Abstract: A power manager of an apparatus exposes an application programming interface (API) usable for applications to specify priority and quality-of-service (QoS) parameters (e.g., bandwidth requirements) for a workload. An application, for instance, specifies the priority and QoS parameters for a workload to be processed using a hardware compute unit. The power manager employs the priority and QoS parameters to configure the bandwidth allocation to access a memory system. In particular, the bandwidth allocation and prioritization are dynamically extended to real-time and best-effort workloads to satisfy specified QoS parameters for inference workloads and improve user experiences.

Abstract: In accordance with the described techniques, a system includes a destination server and a source server configured to migrate a virtual machine running on the source server to the destination server over multiple migration iterations. As part of this, the source server generates first hashes of memory blocks of a memory page allocated to the virtual machine during a first migration iteration of the multiple migration iterations. In addition, the source server generates second hashes of the memory blocks during a second migration iteration of the multiple migration iterations. During the second migration iteration, the source server transfers one or more dirty memory blocks of the memory page that have been modified on the source server since the first migration iteration based on a comparison of the first hashes and the second hashes.