Patents Assigned to ATI Technologies ULC
  • Patent number: 11450058
    Abstract: Techniques for performing ray tracing operations are provided. The techniques include receiving a request to determine whether a ray intersects any primitive of a set of primitives, evaluating the ray against non-leaf nodes of a bounding volume hierarchy to determine whether to eliminate portions of the bounding volume hierarchy from consideration, evaluating the ray against at least one early-termination node not eliminated from consideration, and determining whether to terminate traversal of the bounding volume hierarchy early and to identify that the ray hits a primitive, based on the result of the evaluation of the ray against the at least one early-termination node.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: September 20, 2022
    Assignee: ATI Technologies ULC
    Inventor: Guennadi Riguer
  • Patent number: 11445214
    Abstract: Techniques are provided for determining variance of a pixel block in a frame of video based on variance of pixel blocks in a reference frame of the video, instead of directly, for example, by calculating variance based on pixel values of the pixel block. The techniques include identifying a motion vector for a pixel block in a current frame, the motion vector pointing to a pixel block in a reference frame. The techniques also include determining the cost associated with the motion vector and comparing the cost to first and second thresholds. The techniques include determining the variance for the pixel block of the current frame based on the comparison of the cost to the first and second threshold and based on the variance of the pixel block of the reference frame.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: September 13, 2022
    Assignee: ATI Technologies ULC
    Inventor: Mehdi Saeedi
  • Patent number: 11443715
    Abstract: A display system includes a rendering device and a display device. The rendering device is to render a sequence of frames for display at the display device, wherein the display device is to use an illumination strobe during each frame period associated with a corresponding frame of the sequence of frames. The rendering device further is to determine a position of the illumination strobe within each frame period based one or more input parameters, each input parameter representing a corresponding operational characteristic of one of the rendering device or the display device.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 13, 2022
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Ed Callway, David Glen
  • Patent number: 11443051
    Abstract: A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 13, 2022
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Benjamin Koon Pan Chan, William Lloyd Atkinson, Tung Chuen Kwong, Guhan Krishnan
  • Patent number: 11435806
    Abstract: Automatic voltage reconfiguration in a computer processor including one or more cores includes executing one or more user-specified workloads; determining, based on the user-specified workloads, a respective minimum safe voltage for each core of one or more cores; and modifying a respective voltage configuration for each core of the one or more cores based on the respective minimum safe voltage.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 6, 2022
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Jerry A. Ahrens, Amitabh Mehra, Anil Harwani, William R. Alverson, Grant E. Ley, Charles Sy Lee
  • Publication number: 20220277508
    Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.
    Type: Application
    Filed: May 16, 2022
    Publication date: September 1, 2022
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
  • Patent number: 11430409
    Abstract: A display system includes a rendering device and a display device. The rendering device is to render a sequence of frames for display at a frame rate and to set an illumination configuration to be applied by the display device during a frame period for each frame of the sequence of frames based on the frame rate. The illumination configuration controls at least one of an illumination level and a duration for an illumination strobe, and at least one of an illumination level for an illumination fill preceding the illumination strobe in the frame period and an illumination level for an illumination fill following the illumination strobe in the frame period. The display device is to receive a representation of the illumination configuration from the rendering device and apply the illumination configuration during a frame period for each frame of the sequence of frames to display the frame.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: August 30, 2022
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Ed Callway, David Glen
  • Patent number: 11430410
    Abstract: A display system modifies display cycles of one or more displays to perform a system operation while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods of the one or more displays such that blanking periods equal or exceed a blackout duration and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: August 30, 2022
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Jun Lei, Syed Athar Hussain, David I. J. Glen, Rajeevan Panchacharamoorthy, Fatemeh Amirnavaei, David Galiffi, Arshad Rahman, Boris Ivanovic
  • Patent number: 11424761
    Abstract: An electronic device includes a decoding subsystem having a symbol decoder and a second symbol resolver with a plurality of local symbol decoders and a symbol selector. The symbol decoder outputs a first symbol decoded from an initial code for which a symbol is available in a block of the compressed data. The second symbol resolver decodes, in each local symbol decoder, substantially in parallel with decoding the first symbol in the symbol decoder, a respective symbol from a subsequent initial code for which a symbol is available in a respective sub-block of the block of the compressed data. The second symbol resolver outputs, by the symbol selector, as a second symbol, one of the respective symbols from the local symbol decoders selected by the symbol selector based on the initial code.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: August 23, 2022
    Assignee: ATI Technologies ULC
    Inventor: Vinay Patel
  • Patent number: 11417295
    Abstract: A graphics processing unit (GPU) includes a timing reference one or more processors configured to generate and provide, based on the timing reference, frames to a display system that supports variable refresh rates. The frames include a vertical blanking region having a first duration. The display system transmits information indicating an operation to be performed by the display system during the vertical blanking region of one or more subsequent frames. The one or more processors are configured to increase the first duration to a second duration in response to receiving the information indicating an operation to be performed by the display system during the vertical blanking region of at least one subsequent frame. In some cases, the first duration of the vertical blanking region is a minimum duration that corresponds to a maximum refresh rate supported by the display system.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: August 16, 2022
    Assignee: ATI TECHNOLOGIES ULC
    Inventor: David I. J. Glen
  • Patent number: 11379941
    Abstract: Improvements in the graphics processing pipeline are disclosed. More specifically, a new primitive shader stage performs tasks of the vertex shader stage or a domain shader stage if tessellation is enabled, a geometry shader if enabled, and a fixed function primitive assembler. The primitive shader stage is compiled by a driver from user-provided vertex or domain shader code, geometry shader code, and from code that performs functions of the primitive assembler. Moving tasks of the fixed function primitive assembler to a primitive shader that executes in programmable hardware provides many benefits, such as removal of a fixed function crossbar, removal of dedicated parameter and position buffers that are unusable in general compute mode, and other benefits.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: July 5, 2022
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Todd Martin, Mangesh P. Nijasure, Randy W. Ramsey, Michael Mantor, Laurent Lefebvre
  • Publication number: 20220207644
    Abstract: Data processing methods and devices are provided. A processing device comprises memory and a processor. The memory, which comprises a cache, is configured to store portions of data. The processor is configured to issue a store instruction to store one of the portions of data, provide identifying information associated with the one portion of data, compress the one portion of data; and store the compressed one portion of data across multiple lines of the cache using the identifying information. In an example, the one portion of data is a block of pixels and pixels and the processor is configured to request pixel data for a pixel of a compressed block of pixels, send additional requests for data for other pixels determined to belong to the compressed pixel block and provide an indication that the requests are for pixel data belonging to the compressed block of pixels.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Sergey Korobkov, Jimshed B. Mirza, Anthony Hung-Cheong Chan
  • Publication number: 20220206831
    Abstract: A method and system for managing applications on a virtual machine includes creating a plurality of virtual machines on a computer system. Each virtual machine is isolated from one another. Resources are allocated to each virtual machine based upon a resource requirement of an application executing on each virtual machine.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicant: ATI Technologies ULC
    Inventors: Vignesh Chander, Rohit S. Khaire
  • Publication number: 20220210432
    Abstract: A processing apparatus and video encoding method are provided which include receiving a portion of a video sequence and determining complexities for blocks of pixels of the portion of the video sequence. Quantization parameter values for corresponding blocks of pixels are selected based on complexities of the corresponding blocks and visually perceived coding artifacts of the corresponding blocks produced by the quantization parameter values. The blocks of pixels are encoded, using the selected quantization parameter values. The blocks of pixels are decoded and the portion of the video sequence is provided for display.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicant: ATI Technologies ULC
    Inventors: Feng Pan, Crystal Yeong-Pian Sau, Wei Gao, Mingkai Shao, Dong Liu, Ihab M. A. Amer, Gabor Sines
  • Publication number: 20220207783
    Abstract: Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to receive frames of image data comprising sub-frame portions, schedule a first sub-frame portion of a first frame to be processed by a first layer of the convolutional neural network when the first sub-frame portion is available for processing, process the first sub-frame portion by the first layer and continue the processing of the first sub-frame portion by the first layer when it is determined that there is sufficient image data available for the first layer to continue processing of the first sub-frame portion. Processing on a sub-frame portion basis continues for subsequent layers such that processing by a layer can begin as soon as sufficient data is available for the layer.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Tung Chuen Kwong, David Porpino Sobreira Marques, King Chiu Tam, Shilpa Rajagopalan, Benjamin Koon Pan Chan, Vickie Youmin Wu
  • Publication number: 20220210429
    Abstract: Methods and devices are provided for encoding video. By using co-sited gradient and variance values to detect text and line in frames of the video. A processor is configured to receive a plurality of frames of video, determine, for a portion of a frame, a variance of the portion of the frame and a gradient of the portion of the frame and encode, using one of a plurality of different encoding qualities, the portion of the frame based on the gradient and the variance of the portion of the frame. Encoding is performed at both the sub-frame level and frame level. The portion of the frame is classified into one of a plurality of categories based on the gradient and variance and encoded based on the category.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Applicant: ATI Technologies ULC
    Inventors: Mehdi Saeedi, Sai Harshita Tupili, Yang Liu, Mingkai Shao, Gabor Sines
  • Patent number: 11368692
    Abstract: Systems, apparatuses, and methods for generating a model for determining a quantization strength to use when encoding video frames are disclosed. A pre-encoder performs multiple encoding passes using different quantization strengths on a portion or the entirety of one or more pre-processed video frames. The pre-encoder captures the bit-size of the encoded output for each of the multiple encoding passes. Then, based on the multiple encoding passes, the pre-encoder generates a model for mapping bit-size to quantization strength for encoding video frames or portion(s) thereof. When the encoder begins the final encoding pass for one or more given video frames or any portion(s) thereof, the encoder uses the model to map a preferred bit-size to a given quantization strength. The encoder uses the given quantization strength when encoding the given video frame(s) or frame portion(s) to meet a specified bit-rate for the encoded bitstream.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 21, 2022
    Assignee: ATI Technologies ULC
    Inventors: Jinbo Qiu, Yang Liu, Ihab Amer, Lei Zhang, Edward A. Harold, Zhiqi Hao, Jiao Wang, Gabor Sines, Haibo Liu, Boris Ivanovic
  • Publication number: 20220191070
    Abstract: A receiver circuit includes an analog front end and a non-linear equalizer. The analog front end including a super source follower (SSF) amplifier having a first input terminal adapted to couple to a transmission line to receive an input signal referenced to a first voltage level, a second input adapted to receive a reference voltage, and first and second output terminals adapted to provide an amplified signal referenced to a second voltage level. The non-linear equalizer coupled to receive an output signal of the analog front end and compensate for inter-symbol interference at a data rate of at least 14 Gbps. The SSF amplifier includes transistors having relative sizes selected to provide a frequency response of the SSF amplifier with a peak at a frequency approximately ? of the data rate.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 16, 2022
    Applicant: ATI Technologies ULC
    Inventor: Saman Asgaran
  • Publication number: 20220188180
    Abstract: A method and system for recording and logging errors in a computer system includes reading first error handling information with respect to a transaction. The first error handling information is stored in a first component, and based upon a condition of the storage in the first component, an oldest error information is evicted from the first component.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 16, 2022
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Philip Ng, Buheng Xu
  • Publication number: 20220188139
    Abstract: A technique for managing access to a micro engine, the method comprising: determining that a virtual function “VF”) is to be given access to direct communication with a micro engine; in response to the determining, configuring the micro engine to accept direct communication from the VF; monitoring for unpermitted communication; and after a time period has expired, configuring the micro engine to no longer accept direct communication from the VF.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 16, 2022
    Applicant: ATI Technologies ULC
    Inventors: Yinan Jiang, Kamraan Nasim, Dezhi Ming, Ahmed M. Abdelkhalek, Dmytro Chenchykov, Andy Sung