Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among the multiple functional blocks. When control circuitry detects a low-performance mode, commands are sent to the multiple functional blocks specifying storing data of the given type in a contiguous manner in one or more of the caches of the multiple functional blocks and the memories connected to the multiple functional blocks. Following, the control circuitry transitions the memories to a sleep state and transitions all but one of the functional blocks to the sleep state. The functional blocks rotate amongst themselves with a single functional block being in the active state and servicing requests based on which data of the given type is targeted by the requests.

Abstract: In-system electrical connectivity detection. In one or more implementations, a computing device includes a transmitter and a receiver in a package, the transmitter to transmit a signal to a separate device, the receiver to receive and measure a reflection of the transmitted signal, and the measured reflection for characterizing (e.g., testing or detecting) an electrical connection between the computing and separate devices. The computing device may characterize (e.g., detect a discontinuity in) the electrical connection by comparing a magnitude of the transmitted signal with a magnitude of the measured reflection. The computing device may be coupled with the separate device by multiple electrical connections, and the multiple electrical connections may be tested by corresponding transmitters and receivers.

Abstract: A disclosed system can include (i) a data consumer, (ii) a data producer, and (iii) a virtual channel enabled credit repeater pipeline that connects the data consumer and the data producer across at least both a guaranteed track and an opportunistic track. The virtual channel enabled credit repeater pipeline at the data producer can forward virtual channel data across the opportunistic track based on an amount of credits being insufficient. Various other methods, systems, and apparatuses are also disclosed.

Abstract: A parallel processor assigns data for use by one or more tasks to a shared memory or memories associated with a plurality of compute units. A scheduler or other controller within or otherwise associated with the parallel processor assigns threads or groups of threads, which utilize the assigned data, to compute units as appropriate. Compute units utilize two sets of instructions, one specifying upper bits and one specifying lower bits of a memory address, to specify memory addresses that are larger than a number of bits an individual instruction can specify in a memory address field. Mode setting commands determine when and how lower bits in a memory address field of an instruction will be combined with upper bits in a previous instruction, e.g., through concatenation.

Abstract: A processing unit performs a dispatch walk of a set of thread groups based on a programmable access pattern. The access pattern is stored at a table that is programmed with the access pattern based upon a specified command. By using the command to program the table with different access patterns, the dispatch order of the set of thread groups is adapted to better suit the processing of different data sets, thereby reducing power consumption at the processing unit, and improving overall processing efficiency.

Abstract: A processing system stores a boot image for a critical domain of a system-on-a-chip (SOC) at a bank of a static random-access memory (SRAM) that is shared by the critical domain and a non-critical domain and that is powered independently from the non-critical domain. The SOC includes a secure processor that loads the boot image to the bank of the SRAM and then blocks subsequent write access to the bank. Because the critical domain is powered independently from the non-critical domain, the bank of the SRAM retains the boot image without regard to the power state of the non-critical domain. In addition, the critical domain implements a boot process that is decoupled from a CPU at the non-critical domain, ensuring that the critical domain can initiate a re-boot sequence even if the non-critical domain is not powered.

Abstract: Data integrity checks for reducing communication latency is described. A transmitting endpoint transmits data to a receiving endpoint by generating an integrity tag for a first subset of data blocks and a second integrity tag for a second subset of data blocks. In implementations, the first and second integrity tags overlap at least one data block and are offset based on computational complexities of generating the integrity tags. A receiving endpoint generates comparison tags for each of the integrity tags and uses the comparison tags to validate an authenticity of received data. In response to validating the first and second integrity tags, data blocks covered by both the first and second integrity tags are released for use. Additional integrity tags are generated and validated for subsequent subsets of data blocks during data communication, thus reducing latency by offsetting times at which comparison tags are generated and validated.

Abstract: The disclosed computer-implemented method can include reaching, by a chiplet involved in carrying out an operation for a process, a synchronization barrier. The method can additionally include receiving, by the chiplet, dedicated control messages pushed to the chiplet by other chiplets involved in carrying out the operation for the process, wherein the dedicated control messages are pushed over a control network by the other chiplets. The method can also include advancing, by the chiplet, the synchronization barrier in response to receipt of the dedicated control messages. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A technique for rendering is provided. The technique includes determining a level of detail for a shade space texture and a screen space; shading the shade space texture having a resolution based on the level of detail; and for a reconstruction operation, performing sampling from the shade space texture, the sampling including a high frequency attenuation of samples of the shade space texture.

Abstract: Command stream stitching for hardware acceleration includes generating, by a host processor, a stitched block representing a plurality of commands for a hardware accelerator. The host processor generates a stitched command from the plurality of commands. The stitched command references the stitched block. The hardware accelerator executes the stitched block in response to invoking the stitched command. The hardware accelerator generates a single notification directed to the host processor for the stitched command.

Abstract: A system provides YUV 4:4:4 encoding support in the presence of an encoder or decoder that does not provide native YUV 4:4:4 encoding by generating, at a source device, a plurality of subframes from an input image of a video stream such that each subframe includes a copy of the luminance plane of the input image and a different subset of the chrominance plane of the image plane after chroma subsampling during the encoding process. After decoding the plurality of subframes, a sink device can extract a copy of the luminance plane from one of the subframes and replicate the chrominance plane by compositing the different subsets of the chrominance plane from the plurality of decoded subframes, thereby generating an output image with the same chrominance resolution as the input image even though the individual subframes were subjected to sub-4:4:4 chroma sampling during the encoding process.

Abstract: Systems, apparatuses, and methods for implementing efficient power optimization in a computing system are disclosed. A system management unit configured to track computing activity of a computing device while processing each frame of a plurality of frames. The computing activity is tracked at least for a given period of time comprising a plurality of time slices. The system management unit further correlates a time slice associated with a given frame with a time slice associated with at least one previously processed frame from the plurality of frames, based at least in part on the tracked computing activity. The system management unit predicts a clock frequency to render the given frame, based at least in part on the correlation and renders the given frame using the predicted clock frequency.

Abstract: A compute device implements a technique for facilitating selective access to hardware codec resources. The compute device executes, in a trusted execution environment, firmware for controlling graphics hardware of a device that supports a plurality of video codecs. The compute device obtains codec control data specific to the device from a remote system and then configures the firmware to implement a codec policy for selectively providing access to the plurality of video codecs based on the codec control data.

Abstract: Temporary system adjustment for component overclocking is described. In accordance with the described techniques, a processor and/or memory are operated according to first settings. During operation of the processor and/or the memory according to the first settings, a signal triggers a temporary adjustment of operation of the processor and/or the memory according to second settings. Responsive to the request, operation of the processor and/or the memory is switched to the second settings without rebooting. After a duration, operation of the processor and/or the memory is switched back to the first settings. In one or more implementations, at least one of the first settings or the second settings overclock the processor and/or the memory.

Abstract: A computing system includes a display controller and a processing device external to the display controller. The display controller includes a content verification circuit configured to generate a derived value representing visual content of interest (COI) within an image frame for a region of interest (ROI) on at least one display device. The processing device includes an error-detection circuit configured to perform an error-detection process for the visual COI based on the derived value.

Abstract: The disclosed device includes a direct memory access (DMA) engine having multiple backends and a frontend. The frontend receives a memory operation command, selects one of the backends based on an affinity of the selected backend corresponding to the memory operation command, and instructing the selected backend to perform the memory operation command. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method for clock distribution network control includes determining, at a first clock node of a plurality of clock nodes within a clock distribution network, a downstream clock request status. A clock request signal is transmitted by the first clock node to an upstream parent node based on the downstream clock request status. A clock buffer of the first clock node is toggled based at least in part on the clock request signal to the parent node. If the first clock node receives an asserted clock request signal from one or more downstream child nodes and clock acknowledgment signal from the parent node, a clock enable signal is asserted to the clock buffer to output a clock signal to the one or more downstream child nodes.

Abstract: A computer-implemented method for enabling a feature of a semiconductor device can include receiving, by at least one processor of a semiconductor device, a command to enable a feature of the semiconductor device. The method can also include burning, by the at least one processor and in response to the command, an electronic fuse of the semiconductor device. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed air core inductor array includes a top plate positioned in a first plane and a bottom plate positioned in a second plane. The disclosed air core inductor array additionally includes a plurality of air core inductors arranged between the top plate and the bottom plate, wherein the top plate and the bottom plate form a mutual inductor. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Computing system power surge mitigation is described. In one or more implementations, a processing device includes a hardware kernel that manages power consumption of the processing device by injecting stateless instructions into a processing pipeline. In one or more implementations, a system includes a hardware kernel configured to generate stateless instructions, and a processing device configured to manage power consumption of the system by executing the stateless instructions generated by the hardware kernel.