Abstract: A chip package includes a package substrate, an integrated circuit (IC) die disposed on the package substrate, and a lid assembly disposed over the IC die. The lid assembly includes a top plate having a lower surface facing the IC die and an outer shoulder. The lid assembly also includes a retainer having a lower surface secured to the package substrate and an inner shoulder retaining to the outer shoulder. The inner shoulder is configured to limit upward movement of the top plate, and expansion of the retainer is decoupled from expansion of the top plate.

Abstract: The disclosed device provides ringing mitigation. The device, for example, is a working group processor including a local controller that measures the voltage level within the device and compares the voltage level to a threshold voltage level. If the controller determines that the voltage level is less than the threshold voltage level, the controller determines that a voltage-related event, such as a voltage droop, is occurring within the device. In response to detection of the voltage-related event, the controller selects and injects a stall pattern to stall workloads being processed by the device. The reduction in workloads reduces an activity counter, which thereby mitigates ringing within the device. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An efficient confidential compute check is described. In one or more implementations, an apparatus includes a plurality of processors each configured to execute memory translations of at least one client that map client virtual memory to corresponding allocations of a physical memory shared among the plurality of processors. The apparatus also includes a security circuit configured to authorize client access to allocated regions of the physical memory based on whether an intercepted memory translation corresponds to an authorized client.

Abstract: Digital cameras include an image sensor and an image signal processor. The image signal processor processes raw image data received with the image sensor, accounting for a variety of effects such lens characteristics, Bayer filter color bias, white balance, color intensity effects, or gamma effects. While it is possible to perform this process at the full resolution of the image, advantage can be gained by performing such processing at a higher resolution within a region of interest and at a lower resolution outside the region of interest. In some examples, an image signal processor includes a portion that performs image signal processing on a down-sampled version of the raw image, as well as a high-resolution portion that performs processing on the normal resolution raw image to generate an output image. This technique reduces the overall work needed to process an image received from an image sensor.

Abstract: Techniques are described for adaptive device power management. The device interface application of a hardware computing unit detects a launch of an application by the operating system (OS) to be executed on the hardware computing unit, in an implementation. The device interface application identifies the launched application and determines whether a hardware profile exists that is associated with the application. The hardware profile includes one or more hardware parameters that yield the optimal performance for power consumption by the hardware computing unit when executing the launched application. Based on determining that the hardware profile exists, the power policy of the OS is updated for the launched application, and thereby, the driver updates the power state(s) of the hardware computing unit based on the new power policy.

Abstract: Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to determine, for an input tile of an image, a receptive field via backward propagation and determine a size of the input tile based on the receptive field and an amount of local memory allocated to store data for the input tile. The processor determines whether the amount of local memory allocated to store the data of the input tile and padded data for the receptive field.

Abstract: An apparatus and method for efficiently managing jobs of a workload performed among multiple integrated circuits in separate semiconductor chips. In various implementations, a computing system includes a first processing node and a second processing node that together render and present video frame data. The graphics application holds the start of processing the next video frame until the first processing node receives result data for the current video frame from the second processing node and presents the video frame data. To remove latency, once the result data is generated, the first processing node performs a mocked present job visible to the operating system scheduler but sends no data to the display controller. The rendering of the next video frame begins, and the first processing node later presents the result data to the display controller.

Abstract: An address translation buffer or ATB is provided for emulating or implementing the PCIe (Peripheral Component Interface Express) ATS (Address Translation Services) protocol within a PCIe-compliant device. The ATB operates in place of (or in addition to) an address translation cache (ATC), but is implemented in firmware or hardware without requiring the robust set of resources associated with a permanent hardware cache (e.g., circuitry for cache control and lookup). A component of the device (e.g., a DMA engine) requests translation of an untranslated address, via a host input/output memory management unit for example, and the response (including a translated address) is stored in the ATB for use for a single DMA operation (which may involve multiple transactions across the PCIe bus).

Abstract: A host processing system assigns unequal time slices at a parallel processor to virtual functions based on profiles of applications executing at the virtual functions and an available budget of the parallel processor. The host processing system calculates a world switch cycle interval and assesses an available processing budget of the parallel processor. The available budget indicates the amount of graphics processing time the parallel processor has not yet allocated to virtual functions for each world switch cycle interval.

Abstract: Methods and devices are provided for processing data using a neural network. Activations from a previous layer of the neural network are received by a layer of the neural network. Weighted values, to be applied to values of elements of the activations, are determined based on a spatial correlation of the elements and a task error output by the layer. The weighted values are applied to the values of the elements and a combined error is determined based on the task error and the spatial correlation.

Abstract: An apparatus includes a storage location that is accessible to control plane circuitry and first circuitry configured to receive an interrupt indicating a fatal error. The first circuitry is also configured to provide, in response to the interrupt, first information indicating the fatal error to a data plane entity and second information indicating the fatal error to the storage location. The second information in the storage location is accessible via a control plane connection independently of the data plane entity initiating one or more recovery actions in response to receiving the first information. A system management controller (SMC) or a baseboard management controller (BMC) can be configured to access the second information in the storage location and convey the second information to control plane circuitry in a data center.

Abstract: Systems and methods for aligning flits including an apparatus or device including a first circuit corresponding to a data link layer, and a second circuit corresponding to a physical layer, the second circuit including a first sublayer, a second sublayer located between the first sublayer and an interconnect link, and an interface communicatively coupling the first sublayer to the second sublayer for transmission of code blocks between the first and second sublayers during data communications between the link partners, the code blocks align a first datagrams of the first sublayer to a second datagrams of the second sublayer based on alignment markers of the second datagrams. In a transmit direction, the first sublayer sends first code blocks to the second sublayer to indicate when to overwrite the alignment markers. In a receive direction, the second sublayer sends second code blocks to indicate when the first datagrams include alignment markers.

Abstract: Systems and methods for reducing, by a link partner, backlog at a receiver buffer of the other link partner. Each link partner includes at least one circuit coupled between a data fabric and an interconnect link of an interconnect fabric. The at least one circuit includes a receiver configured to receive datagrams from the interconnect fabric and a transmitter configured to send datagrams over the interconnect fabric. The transmitter is configured to monitor a loop latency for datagrams communicated between the link partners over the interconnect fabric using toggling handshake codes in their headers. Based on the monitored loop latency for the datagrams, the transmitter of a link partner is configured to reduce a receiver buffer backlog at the other link partner. The loop latency monitoring can include monitoring an unloaded and loaded loop latencies and comparing a difference between the loop latencies to one or more thresholds.

Abstract: Systems and devices for packing one or more sequence numbers into datagrams for transmission to a link partner over an interconnect fabric, the link partners including a transmitter in communication with a receiver for data transmission over the interconnect link, each of the transmitter and the receiver including at least one circuit. The at least one circuit packages a header and a data payload into data packets for transmission to the other of the transmitter and the receiver. Responsive to a request from the transmitter or the receiver, the at least one circuit of the transmitter or the receiver encodes a first sequence number and a second sequence number into the header of the data packet for transmission to the other of the transmitter or the receiver. The first sequence number may be a transmitter sequence number, and the second sequence number may be a receiver sequence number.

Abstract: Systems and devices for Universal Asynchronous Receiver Transmitter (UART) mode communication may include a first circuit including a first receiver transmitter in communication with a second receiver transmitter of a second circuit over an interconnect link. In a transmit direction, the first circuit is configured to pack stream transport data into data flits of a datagram for serialized transmission of data from the first receiver transmitter to the second receiver transmitter over the interconnect link. In a receive direction, the first circuit is configured to unpack the stream transport data from the data flits received as serialized data over the interconnect link from the second circuit of the second receiver transmitter. The stream transport data can be firmware data packed into the data flits as data link messages, which may be exchanged between firmware agents associated with the respective first circuit and second circuit.

Abstract: Systems and devices for packaging first data flits into second data flits may include at least one circuit of a first processor. In a transmit direction, the at least one circuit receives first data flits and packages the data of the first data flits into second data flits for transmission to at least one second processor over an interconnect link. In a receive direction, the at least one circuit receives a second data flit and packages the data into one or more first data flits for transmission to the first processor. The first data flit and second data flit may be a transaction layer flit and data layer flit, respectively. The second data flit may include a flit header, a cyclic redundancy check, and a plurality of segments, each segment including a segment header, an integer number of sectors, and one or more portions for storing the first data flits.

Abstract: An apparatus and method for efficiently managing performance among replicated modules of an integrated circuit despite manufacturing variations across semiconductor dies. An integrated circuit includes a first module with a first partition of multiple dies that share at least a same first power rail. The integrated circuit also includes a second module with a second partition of multiple dies that share at least a same second power rail different from the first power rail. The dies within partitions have differences in circuit parameters within a threshold such that the dies can be placed in a same first bin. The dies in different partitions belong to different bins. A power manager initially assigns the same operating parameters to the first partition and the second partition, but adjusts the operating parameters based on detection of the different circuit behavior due to manufacturing variations between the first partition and the second partition.

Abstract: An electronic device that includes a decompression engine that includes N decoders and a decompressor decompresses compressed input data that includes N streams of data. Upon receiving a command to decompress compressed input data, the decompression engine causes each of the N decoders to decode a respective one of the N streams from the compressed input data separately and substantially in parallel with others of the N decoders. Each decoder outputs a stream of decoded data of a respective type for generating commands associated with a compression standard for decompressing the compressed input data. The decompressor next generates, from the streams of decoded data output by the N decoders, commands for decompressing the data using the compression standard to recreate the original data. The decompressor next executes the commands to recreate the original data and stores the original data in a memory or provides the original data to another entity.

Abstract: A quantum dot liquid crystal display has a backlight generated by a light emitting diode (“LED”) that is typically blue and a quantum dot film that performs color conversion to red and green to produce white light. While cheap and efficient, the LEDs in such displays illuminate the pixels unevenly, and the distribution of uneven illumination is different for different wavelengths of light (e.g., red, green, and blue). A technique to compensate for this aspect includes measuring certain optical characteristics of the uneven illumination distribution, processing such measurements, and applying the results of such processing to the “desired” input image to generate an output image for display.

Abstract: An efficient confidential compute check is described. In one or more implementations, an apparatus includes a plurality of processors each configured to execute memory translations of at least one client that map client virtual memory to corresponding allocations of a physical memory shared among the plurality of processors. The apparatus also includes a security circuit configured to authorize client access to allocated regions of the physical memory based on whether an intercepted memory translation corresponds to an authorized client.