Abstract: A method can include overriding settings of an integrated circuit device by reading one or more settings from a setting record that correspond to a part number of the integrated circuit device. The method can also include performing an override of the settings of the integrated circuit device based on the one or more settings of the setting record that correspond to the part number of the integrated circuit device. Various other methods and systems are also disclosed.

Abstract: A method for synchronizing trusted operating systems can include receiving, at a first interconnect circuit, an operating system management instruction for a first trusted operating system that is associated with a first trusted memory region of a memory device, the first trusted memory region being allocated to the first interconnect circuit. The method can also include synchronizing the operating system management instruction with a second interconnect circuit such that the operating system management instruction is applied to a second trusted operating system. The second trusted operating system is associated with a second trusted memory region of the memory device and the second trusted memory region is allocated to the second interconnect circuit. Various other methods and systems are also disclosed.

Abstract: The disclosed device can receive a biosignal and, using user input predictions based on the biosignal, pre-render a display frame. The device can also subsequently receive a user input, output the pre-rendered display frame based on the user input confirming the user input predictions and flush the pre-rendered display frame otherwise. The device can also modulate computing performance and power based on computing demands predicted from the biosignal. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.

Abstract: An apparatus and method for efficiently managing performance among multiple integrated circuits in separate semiconductor chips. In various implementations, a computing system includes at least a first processing node and a second processing node. While processing tasks, the first processing node accesses a first memory and the second processing node accesses a second memory. A first communication channel transfers data between the first and second processing nodes. The first processing node accesses the second memory using a second communication channel different from the first communication channel and supports point-to-point communication. The second memory services access requests from the first and second processing nodes as the access requests are received while foregoing access conflict detection. The first processing node accesses the second memory after a particular amount of time has elapsed after reception of an indication from the second processing node specifying that a particular task has begun.

Abstract: A computer-implemented method for enabling a feature of a semiconductor device can include receiving, by at least one processor of a semiconductor device, a command to enable a feature of the semiconductor device. The method can also include burning, by the at least one processor and in response to the command, an electronic fuse of the semiconductor device. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A computer-implemented method for ensuring processing unit hardware state integrity in live migration can include participating as a source, by a processing unit, in a live migration procedure by injecting, into a live migration data package containing a state of the processing unit, a signature verifying the state. The method can additionally include participating as a target, by the processing unit, in an additional live migration procedure migrating an additional live migration data package containing an additional state of an additional processing unit by performing an integrity check based on an additional signature, in the additional live migration data package, verifying the additional state. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A technique for performing ray tracing operations is provided. The technique includes for a ray being tested for intersection with geometry associated with a bounding volume hierarchy, traversing to a pre-filtering node that includes information for filtering out triangles of a leaf node of the bounding volume hierarchy; evaluating a quantized ray that corresponds to the ray against quantized triangles of the pre-filtering node to filter out one or more triangles of the leaf node from consideration; and testing the triangles of the leaf node that are not filtered out and not testing the triangles of the leaf node that are filtered out.

Abstract: A technique for rendering is provided. The technique includes performing a visibility operation to generate shade space visibility information and reconstruction information; performing a shade space shading operation based on the shade space visibility information generate shaded shade space textures; and performing a reconstruction operation based on the reconstruction information and the shaded shade space textures.

Abstract: Devices and methods for rendering objects using ray tracing are provided which include during a build time: generating an accelerated hierarchy structure comprising data representing an approximate volume bounding a group of geometric shapes representing the objects in the scene and data representing the geometric shapes; and generating additional data used to transform rays, to be cast in the scene, from a high precision space to a low precision space; and during a render time occurring after the build time: performing ray intersection tests, using the additional data generated during the build time, for the rays in the scene; and rendering the scene based on the ray intersection tests. Because the additional data is generated prior to render time, the additional data can be used to perform the ray intersection testing more efficiently.

Abstract: A technique for rendering is provided. The technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover the shade space textures visible in the scene; performing a temporal rate controller operation; performing a shade space shading operation on the tiles that cover the shade space textures visible in the scene based on a temporal shading rate output by the temporal rate controller operation, wherein only a subset of samples in the tiles that cover the shade space textures visible in the scene are shaded in the shade space shading operation; and performing a reconstruction operation using output from the shade space shading operation to produce a final scene.

Abstract: A technique for rendering is provided. The technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover shade space textures visible in the scene; performing a rate controller operation on output of the visibility pass using spatially-adaptive sampling; performing a sparse shade space shading operation on the tiles that cover the shade space textures visible in the scene based on a result of the spatially-adaptive sampling; performing a regularization operation based on an output of the sparse shade space shading operation; and performing a reconstruction operation using output from the regularization operation to produce a final scene.

Abstract: A technique for rendering is provided. The technique includes determining a level of detail for a shade space texture and a screen space; shading the shade space texture having a resolution based on the level of detail; and for a reconstruction operation, performing sampling from the shade space texture, the sampling including a high frequency attenuation of samples of the shade space texture.

Abstract: A technique for rendering is provided. The technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover shade space textures visible in the scene; performing a rate controller operation on output of the visibility pass using spatiotemporal adaptive sampling; performing a shade space shading operation on the tiles that cover the shade space textures visible in the scene based on a result of the spatiotemporal adaptive sampling; performing a regularization operation based on an output of the shade space shading operation; and performing a reconstruction operation using output from the regularization operation to produce a final scene.

Abstract: A method and computing device is provided for filtering objects of interest of images. The computing device comprises an image capturing device and memory configured to store objects of interest. In one example, the computing device comprises a processor configured to, for a captured image, determine one or more regions of interest in the image based on the objects of interest and modify the image based on the determined regions of interest. In another example, the computing device comprises a first processor configured to determine one or more regions of interest to be modified in an image based on the one or more objects of interest and a second processor configured to convert the image to be processed by the first processor and modify the image based on regions of interest determined by the first processor. The image is displayed without the one or more objects of interest being viewable.

Abstract: A technique for performing video operations is provided. The technique includes characterizing a frame as a flash frame; setting the flash frame as a non-intra frame; prohibiting encoding of frames other than the flash frame with reference to the flash frame; and applying a positive quantization parameter (“QP”) offset to the flash frame.

Abstract: Systems, apparatuses, and methods for achieving higher cache hit rates for machine learning models are disclosed. When a processor executes a given layer of a machine learning model, the processor generates and stores activation data in a cache subsystem a forward or reverse manner. Typically, the entirety of the activation data does not fit in the cache subsystem. The processor records the order in which activation data is generated for the given layer. Next, when the processor initiates execution of a subsequent layer of the machine learning model, the processor processes the previous layer's activation data in a reverse order from how the activation data was generated. In this way, the processor alternates how the layers of the machine learning model process data by either starting from the front end or starting from the back end of the array.

Abstract: A computer-implemented method for ensuring processing unit hardware state integrity in live migration can include participating as a source, by a processing unit, in a live migration procedure by injecting, into a live migration data package containing a state of the processing unit, a signature verifying the state. The method can additionally include participating as a target, by the processing unit, in an additional live migration procedure migrating an additional live migration data package containing an additional state of an additional processing unit by performing an integrity check based on an additional signature, in the additional live migration data package, verifying the additional state. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Graphics processing unit (GPU) selection based on a utilized power source, including: determining that an apparatus is using a direct current (DC) power source instead of an Alternating Current (AC) power source; and causing, in response to the apparatus using the DC power source, the apparatus to preferentially utilize an integrated graphics processing unit (iGPU) over a discrete graphics processing unit (dGPU) while using the DC power source.

Abstract: The disclosed computing device can include host circuitry configured to provide a physical function and guest circuitry configured to provide a virtual function. The host circuitry is configured to dynamically assign request identifiers for accessing at least the host circuitry in a manner that allows the request identifiers to change on a command-to-command basis instead of a time-to-time basis that uses fixed value request identifiers in time slices. Various other methods, systems, and computer-readable media are also disclosed.