Abstract: A memory module performs a memory readiness test, and reports results to a host system. The memory module initializes a status register with an initial ready time value and a memory readiness status. The memory module conducts the memory readiness test, and while conducting the memory readiness test, estimates a new ready time based on the progress of the memory readiness test. The memory module updates the ready time value in the status register based on the new ready time. After finishing the memory readiness test, the memory module updates the memory readiness status in the status register.

Abstract: A technique for generating encoded video in a client-server system is provided. According to the technique, a server determines that reprojection analysis should occur. The server generates reprojection metadata based on suitability of video content to reprojection. The server generates encoded video based on the reprojection metadata, and transmits the encoded video to a client for display. The client reprojects video content as directed by the server.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.

Abstract: A technique for improving performance of a cache is provided. The technique involves maintaining indicators of whether cache entries are dirty in a random access memory (“RAM”) that has a lower latency to a cache controller than the cache memory that stores the cache entries. When a request to invalidate one or more cache entries is received by the cache controller, the cache controller checks the RAM to determine whether any cache entries are dirty and thus should be written out to a backing store. Using the RAM removes the need to check the actual cache memory for whether cache entries are dirty, which reduces the latency associated with performing such checks and thus with performing cache invalidations.

Abstract: Techniques for removing or identifying overlapping fragments in a fragment stream after z-culling are disclosed. The techniques include maintaining a first-in-first-out buffer that stores post-z-cull fragments. Each time a new fragment is received at the buffer, the screen position of the fragment is checked against all other fragments in the buffer. If the screen position of the fragment matches the screen position of a fragment in the buffer, then the fragment in the buffer is removed or marked as overlapping. If the screen position of the fragment does not match the screen position of any fragment in the buffer, then no modification is performed to fragments already in the buffer. In either case, he fragment is added to the buffer. The contents of the buffer are transmitted to the pixel shader for pixel shading at a later time.

Abstract: An endpoint processing device is provided for dynamically controlling latency tolerance reporting (LTR) values. The endpoint processing device comprises memory configured to store data and a processor. The processor is configured to execute a program and send, to a root point processing device via a peripheral component interconnect express (PCIe) link, a plurality of messages each comprising a memory access request and a LTR value indicating an amount of time to service the memory access request. The processor is also configured to, for each of the plurality of messages, determine, during execution of the program, a LTR value setting and set the LTR value as the determined LTR value setting.

Abstract: A method and apparatus for determining link bifurcation availability implemented in a computer system includes assigning, by a controller, lanes that include links for one or more components connected in accordance with a current known configuration. The controller transmits ordered sets including the assignments to the one or more components which are received by the one or more components. The one or more components respond with a first link to the controller. Based upon the links received by the controller not meeting the current known configuration, the controller issues an interrupt and is reconfigured.

Abstract: Systems, apparatuses, and methods for calculating a quantization parameter (QP) for encoding video frames to meet a given bit budget are disclosed. Control logic coupled to an encoder calculates a complexity indicator that represents a level of difficulty in encoding a previous video frame. The complexity indicator is based at least in part on a first parameter associated with the previous video frame and corresponds to one or more of a variance, an intra-prediction factor, and an inter-to-intra ratio. The complexity indicator is then used by the control logic to calculate a preferred QP to use to encode the current video frame to meet a given bit budget. By using the preferred QP generated based on the complexity indicator, the encoder is able to make fewer QP adjustments during the frame. This helps to improve the visual quality of the resulting encoded video bitstream.

Abstract: A processing unit includes a processor core that implements a physical function that supports multiple virtual functions. The processing unit includes a bus interface that supports communication between an external bus and the physical and virtual functions implemented using the processor core. During a reset of the processing unit, power is interrupted to the processor core power to the bus interface is maintained. The bus interface responds to requests for the physical and virtual functions received over the external bus concurrently with the power interruption. The bus interface responds based on state information associated with the virtual function. Power is restored to the processor core in response to the reinitialization of the GPU. The bus interface stops responding to requests for the physical and virtual functions received over the bus interface in response to restoring the power to the processor core and forwards requests received over the external bus from the bus interface to the processor core.

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first molding layer and has plural conductor structures electrically connected to the plural conductor traces. The plural conductor traces provide lateral routing.

Abstract: An electronic device for decompressing compressed data includes a decoding subsystem having a symbol decoder and a second symbol resolver with a number of local symbol decoders and a symbol selector. The symbol decoder decodes a first symbol from a first code for which a symbol is available in a block of the compressed data and communicates a length of the code to the second symbol resolver. Each local symbol decoder, substantially in parallel with the decoding of the first symbol in the symbol decoder, decodes a respective symbol from a first code for which a symbol is available in a respective sub-block of the block of the compressed data. The second symbol resolver selects, as a second symbol, based on the length received from the symbol decoder, one of the respective symbols from the local symbol decoders. The decoding subsystem then provides the first and second symbols.

Abstract: A technique for scheduling processing tasks having different latencies is provided. The technique involves identifying one or more available requests in a request queue, where each request queue corresponds to a different latency. A request arbiter examines a shift register to determine whether there is an available slot for the one or more requests. A slot is available for a request if there is a slot that is a number of slots from the end of the shift register equal to the number of cycles the request takes to complete processing in a corresponding processing pipeline. If a slot is available, the request is scheduled for execution and the slot is marked as being occupied. If a slot is not available, the request is not scheduled for execution on the current cycle. On transitioning to a new cycle, the shift register is shifted towards its end and the technique repeats.

Abstract: An electronic device includes a processor that executes a guest operating system, an input-output memory management unit (IOMMU), and a main memory that stores an IOMMU backing store. The IOMMU backing store includes a separate copy of a set of IOMMU memory-mapped input-output (MMIO) registers for each guest operating system in a set of supported guest operating systems. The IOMMU receives, from the guest operating system, a communication that accesses data in a given IOMMU MMIO register. The IOMMU then performs a corresponding access of the data in a copy of the given IOMMU MMIO register in the IOMMU backing store associated with the guest operating system.

Abstract: A data transmission medium includes first and second conductors and a first reversible plug connector coupled to a first end thereof. The first reversible plug connector includes a plurality of signal pins, a crossbar switch, a receiver, and a transmitter. In response to a first configuration state, the plurality of signal pins includes a first predetermined number of reception pins and a second predetermined number of transmission pins. The first and second predetermined numbers are different from each other and each is greater than zero. The crossbar switch couples the first predetermined number of reception pins to a first port and the second predetermined number of transmission pins to a second port. The receiver has an input coupled to the first conductor, and an output coupled to the first port. The transmitter has an input coupled to the second port and an output coupled to the second conductor.

Abstract: A method and apparatus for determining link bifurcation availability implemented in a computer system includes assigning, by a controller, lanes that include links for one or more components connected in accordance with a current known configuration. The controller transmits ordered sets including the assignments to the one or more components which are received by the one or more components. The one or more components respond with a first link to the controller. Based upon the links received by the controller not meeting the current known configuration, the controller issues an interrupt and is reconfigured.

Abstract: There are many instances where a standard dynamic range (“SDR”) overlay is displayed over high dynamic range (“HDR”) content on HDR displays. Because the overlay is SDR, the maximum brightness of the overlay is much lower than the maximum brightness of the HDR content, which can lead to the SDR elements being obscured if those elements have at least some transparency. The present disclosure provides techniques including modifying the luminance of either or both of the HDR and SDR content when an SDR layer with some transparency is displayed over HDR content. A variety of techniques are provided. In one example, a fixed adjustment is applied to pixels of one or both of the SDR layer and the HDR layer. The fixed adjustment comprises decreasing the luminance of the HDR layer and/or increasing the luminance of the SDR layer. In another example, a variable adjustment is applied.

Abstract: A method and apparatus for providing multi-view composed frames uses a single display pipe mechanism. The single display pipe includes, in one example, a memory requestor that fetches multi-view data from a frame buffer using a plurality of viewports. The single display pipe may also include a multi-view packer. Each viewport of the single display pipe has access to a frame buffer holding multi-view frame data, and may be configured to have access to different areas of the frame buffer. In this fashion the single display pipe may fetch data representing more than one view of a multi-view frame. Additionally, the multi-view packer combines the data fetched from one or more of the viewports to form a multi-view frame to be supplied for display.

Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.

Abstract: A GPU is generally configured to detect changes in the rate of frame generation that can result from, for example, changes in the complexity of the frames being generated. In response to detecting the change in the rate of frame generation, the GPU identifies a corresponding change in the refresh rate that would be required to fully synchronize the refresh rate with the rate of frame generation. If the change in the refresh rate falls outside the boundaries of a specified or dynamically generated window, the GPU limits the change in refresh rate to the corresponding boundary.