Abstract: A low power biasing circuit for powering up split-rail electronic circuits includes an intermediate voltage generator at each pad which is supplied by a temporary supply voltage to generate a temporary intermediate voltage only when a power signal indicates that all external voltage rails are not safe, thereby reducing power consumption.

Abstract: An apparatus, computer readable medium, and method of event based dynamic power management. The method includes responding to receiving an indication of an event that is external to a hardware block engine by adjusting the power to the hardware block engine, if the event indicates that the power to the hardware block engine should be adjusted. The method may include receiving a second event that is external to the hardware block engine. The method may include determining whether or not the power should be adjusted to the hardware block engine based on the event and the second event. If it is determined that the power should be adjusted, then the power may be adjusted to the hardware block based on the event and second event. A method of monitoring a component and sending an indication of an event that the component will not require a hardware block engine is disclosed.

Abstract: A method and apparatus determines an activity history context for each of a plurality of virtual machines sharing use of a graphics processing core. Each activity history context provides information related to a power setting of at least one engine of the graphics processing core during at least one prior use of the graphics processing core by the corresponding virtual machine. The method and apparatus controls a power setting of the at least one engine of the graphics processing core based on the activity history context corresponding to an active virtual machine using the graphics processing core.

Abstract: Systems and methods are used to configure a communication channel. A source device can dynamically map Display Port lanes to support both display devices and USB3.0 devices. A method for configuring a communication channel includes detecting a device connection event indicating a change to a configuration of the communication channel in response to a branch device of the communication channel satisfying a dynamic configuration capability criteria indicating that the communication channel is reconfigurable. Configuration parameters of a sink device in the communication channel are identified. The communication channel is reconfigured to carry a source data stream to the sink device based on the configuration parameters.

Abstract: A transmitting interconnect interface inserts clock mismatch compensation symbols into a transmitted data stream so as to allow the receiving interconnect interface to compensate for clock frequency mismatch between transmit-side and receive-side clocks. The transmitting interconnect interface adjusts the rate of insertion of these symbols based on a determination of the clock frequency mismatch. The transmitting interconnect interface can incrementally adjust the insertion rate to change substantially proportionally with changes in the clock frequency mismatch. Alternatively, the transmitting interconnect interface can set the insertion rate to one of two levels. By adapting the insertion rate to the current measured clock frequency mismatch, the bandwidth penalty incurred by transmitting clock mismatch compensation symbols in excess of that necessary to permit receiver clock tolerance compensation can be reduced, thereby permitting more transmit bandwidth to be used for transmitting data.

Abstract: Apparatuses, computer readable mediums, and methods of encoding video are disclosed. A video comprising a plurality of frames is encoded. The method may determine whether to encode a frame as an interframe (I frame) or a predicted frame (P frame). An I frame may be encoded with a quantization parameter (QP), which may be determined for the I frame. A P frame may be encoded with a QP limited to vary between a lower QP and an upper QP. After encoding N P frames, QP may be adjusted, where N is a fixed or dynamically adjusted number of frames. If a number of bits used to encode the N P frames exceeds a first budget threshold then the value of QP may be raised, and if the number of bits used to encode the N P frames is below a second budget threshold then the value of QP may be lowered.

Abstract: A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a display serial interface protocol, and a uni-directional serial link which accords to a camera serial interface protocol. The GMIC receives packets from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a host memory operation and may be connected to a display over a bi-directional serial link and to a camera over a uni-directional serial link and a bi-directional control link allowing the host to control the display and camera.

Abstract: An apparatus and method provides an automated mechanism for configuring a position arrangement of displays in a group of displays, such as a display grid. The apparatus and method uses an image capture unit, such as a camera to capture an image of the entire display grid while test patterns are being provided. In one example, a first device outputs the test patterns to the display grid while a second device that includes the camera analyzes the captured images and determines whether a display in the display grid needs to be logically remapped to provide proper image display when the first device outputs full SLS frames in normal operation.

Abstract: An image processing system and method receives one or more digital images in the form of image data, including selected object data of a digital image, and determines, by an electronic recognition process, if a recognition match is available between the selected object data of the digital image and image object library data associated with image descriptor library data. An automated library user interface presents selectable matched object descriptor data associated with the image descriptor library data when a recognition match occurs between the selected object data of the digital image and the image descriptor library data. In response, the automated library user interface provides user feedback data to confirm that the image descriptor library data corresponds with the selected object data of the digital image, or entered descriptor data if no match or an incorrect match occurs, to create library descriptor associated image data.

Abstract: To adjust brightness of at least a portion of a display image, a type of content to be included within the display image is determined and, based on the identified content type, the light source of the display is set to an adjusted intensity. Thereafter, that portion of the display image unrelated to the content requiring adjusted brightness is processed to account for the adjusted intensity of the light source. Because the processing in accordance with the present invention is performed entirely on one or more processors that provide the display images to the display, the present invention overcomes the added complexity and cost associated with prior art techniques, while simultaneously providing the flexibility to quickly adjust display brightness based on types of content being included in the displayed image.

Abstract: A power converter for a load with varying power requirements dynamically adjusts its supply voltage to the load so as to track the radio frequency (RF) envelope of the signal being carried by the load. The supply voltage can be provided by a multiple-output charge pump providing multiple output voltage levels concurrently, and a switch to provide a selected one of the different output voltage levels as the supply voltage to the load. A controller controls the switch to dynamically modify the voltage level selected for output as the supply voltage such that the supply voltage tracks the RF envelope of the signal being carried by the load. As the switching losses of transistors of the power converter may exceed the power savings achieved through envelope tracking, the power converter employs a peak following frequency divider circuit that limits the switching frequency of the power converter to a threshold frequency.

Abstract: Various computing center control and cooling apparatus and methods are disclosed. In one aspect, a method of controlling plural processors of a computing system is provided. The method includes monitoring activity levels of the plural processors over a time interval to determine plural activity level scores. The plural activity level scores are compared with predetermined processor activity level scores corresponding to preselected processor operating modes to determine a recommended operating mode for each of the plural processors. Each of the plural processors is instructed to operate in one of the recommended operating modes.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced.

Abstract: An apparatus includes a plurality of image processing circuits. Each image processing circuit generates an image frame corresponding to a single large surface. The first image processing circuit provides a portion of the generated image frame for a first display or plurality of displays and provides a remaining portion of the image frame to the remaining image processing circuits. The next image processing circuits provides the remaining portion of the image frame for the next plurality of displays.

Abstract: To apportion desired video processing between a video source device and a video sink device, at one of the devices, and based upon an indication of video processing algorithms of which the other device is capable and an indication of video processing algorithms of which the one device is capable, a set of video processing algorithms for achieving desired video processing is identified. The identified set of video processing algorithms is classified into a first subset of algorithms for performance by the other device and a second subset of algorithms for performance by the one device. At least one command for causing the other device to effect the first subset of video processing algorithms is sent. The one device may be configured to effect the second subset of algorithms.

Abstract: A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer at the first rate, and read from the first and second buffer, at the second rate. Underflow of the first buffer is signaled to the second buffer, thereby avoiding the need to insert defined clock compensation symbols at the second rate. Symbols received at the second buffer while underflow is signaled may be ignored. Conveniently, the second buffer may also be used to align symbol data across multiple symbol streams using periodic alignment symbols. An exemplary embodiment conforms to the PCI Express standard.

Abstract: A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Abstract: An apparatus and method for processing pixel depth information eliminates stalling of data in a pixel pipeline, by performing late Z processing for one or more pixels currently in the pixel pipeline and early Z processing for one or more pixels entering the pixel pipeline. The apparatus and method also includes determining whether the late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The apparatus and method also includes solely performing early Z processing for subsequent pixels entering the pixel pipeline responsive to determining that late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The methods and apparatus, facilitates concurrent processing of early and late Z data to avoid flushing portions of the pixel pipeline.

Abstract: A method and apparatus for configuring multiple displays includes determining, in connection with an image or portion thereof to be displayed on the multiple displays at the same time, whether received display preferences can be fulfilled in observance of: configuration properties of the multiple displays and configuration properties of a computing system, such as the capabilities of display controllers. The method and apparatus also determine whether a current configuration of the multiple displays to the computing system can be reconfigured such that the display preferences of the multiple displays can be fulfilled at the same time while maintaining effective configuration of a current configuration when the display preferences cannot be fulfilled, and display the images of a portion thereof on the multiple displays at the same time.

Abstract: A method and circuitry for determining a temperature-independent bandgap reference voltage are disclosed. The method includes determining a quantity proportional to an internal series resistance of a p-n junction diode and determining the temperature-independent bandgap reference voltage using the quantity proportional to an internal series resistance.