Abstract: In an implementation, a semiconductor chip includes a device layer, an interconnect layer fabricated on the device layer, the interconnect layer including a conductive pad, and a conductive pillar coupled to the conductive pad. The conductive pillar includes at least a first portion having a first width and a second portion having a second width, the first portion being disposed between the second portion and the conductive pad, wherein the first width of the first portion is greater than the second width of the second portion.
Type:
Grant
Filed:
November 17, 2021
Date of Patent:
April 9, 2024
Assignees:
ADVANCED MICRO DEVICES, INC., ATI TECHNOOGIES ULC