Abstract: A clock synchronization unit is provided for an electronic system, particularly for a microprocessor, that includes a first input for a first clock signal, a second input for a second clock signal, a third input for a select control signal, and an output for a system clock signal. A first control module controlled by the first clock signal, a second control module controlled by the second clock signal and connected to the first control module in terms of signaling technique is also provided. The first control module upon application of a predefined signal level of the select control signal at the third input synchronously with the first dock signal, is designed to set the system clock signal from the first clock signal to a predefined logic signal level as the system clock hold signal, and the second control module is designed, synchronously with the second clock signal, to reset the system clock hold signal and to cause an output of the second clock signal as the system clock signal.

Abstract: A high frequency arrangement is provided that includes an integrated high frequency circuit, a first bond pad, which is electrically connected by a first electrical supply line, in particular a bond wire and/or a solder bump, to a housing terminal and/or another circuit, wherein the first bond pad adjoins a dielectric so that the first bond pad forms a first capacitance with the dielectric and an electrically conductive region of the integrated high-frequency circuit, and the first capacitance and the first supply line, which has an inductance, influence a (tuned) first resonant frequency associated with the high-frequency circuit.