Abstract: A successive approximation analog/digital converter is provided, which includes a successive approximation register supplying a digital/analog converter, first means of comparing an input signal of the analog/digital converter to an output signal of the digital/analog converter delivering a first comparison signal, said successive approximation analog/digital converter being synchronised by a clock signal coming from a conversion clock. A method such as this includes dynamic adaptation of the conversion clock period based on at least one parameter.

Abstract: A decoding process, by an electronic circuit of a diphase asynchronous frame carried by an encoded data signal and comprising L information bits followed by at least one stop bit. The process comprises a step for automatically detecting the length L in information bits of the frame so as to decode the entire frame, the length L of the frame being variable from one frame to another and such that Lmin?L?Lmax=(Lmin+k), where k is a predetermined whole number greater than or equal to one.

Abstract: The disclosure relates to a logic cell for an integrated circuit, including two redundant outputs, a first output equipped with an output transistor of type P and a second output equipped with an output transistor of type N. Such a cell includes isolation element connecting the first and second outputs and forming an isolation resistance.

Abstract: A voltage regulator system is provided, which receives a first voltage and produces a regulated voltage. Such a device does not include any transistor supporting the first voltage, but does include transistors supporting at most a second voltage lower than the first voltage and includes division means, which include a first transistor connected in series with at least one second transistor, which division means receive the first voltage and generate the regulated voltage.

Abstract: A device for converting a continuous supply voltage into a continuous output voltage includes at least one inductor accumulating energy during an accumulation time and delivering said accumulated energy during a discharge time, so that said output voltage has a value that is greater than or equal to that of said supply voltage. An oscillator controls said accumulation and discharge times, in which a period is equal to a sum of said accumulation time and said discharge time and a cyclic ratio is equal to the ratio of said accumulation time to said period. The oscillator includes a mechanism for controlling said period and said cyclic ratio according to said supply voltage and said output voltage.

Abstract: This disclosure relates to an electronic driver device for an external load to which an input signal is applied at its input and that produces an output signal to the external load from its output. Such an electronic driver device includes elements that reduce dependence of the slew rate of the output signal on the external load capacitance.

Abstract: A process for automatically detecting and configuring with the throughput of a network, in which a device: (a) goes into a listen mode; (b) obtains a triplet of successive transitions in a transmitted signal, the triplet delimiting first and second signal levels, one dominant and the other recessive; (c) measures the duration of each of the first and second levels; (d) as a function of the measured durations, obtains a new throughput configuration by determining values for parameters that define a bit length LBIT; (e) validates the new throughput configuration; (g) if at least one throughput adaptation condition is verified, goes into a normal mode, otherwise obtains a next transition of the signal, which delimits with the last previous transition a new level of the signal, then measures the duration of the new level and reiterates steps (d) to (g) taking account of the new signal level.

Abstract: An arbitration device is provided, which is designed to be connected between, on the one hand, a first and a second module and, on the other hand, storing means forming a memory workspace. This arbitration device includes a detector for detecting one or more requests coming, concurrently or not, from the first and second modules, for the purpose of accessing the memory workspace.

Abstract: A comparison device includes a one-threshold comparator receiving an input signal and a set value and generating a resultant signal. The comparison device further includes a sampler for sampling the resultant signal and a controller for blocking the sampler, after a switching of the input signal, as long as a timeout mechanism does not indicate that a given timeout duration has elapsed since the verification of a predetermined instability criterion.

Abstract: A successive approximation analog/digital converter is provided, which includes a successive approximation register supplying a digital/analog converter, first means of comparing an input signal of the analog/digital converter to an output signal of the digital/analog converter delivering a first comparison signal, said successive approximation analog/digital converter being synchronised by a clock signal coming from a conversion clock. A method such as this includes dynamic adaptation of the conversion clock period based on at least one parameter.

Abstract: An output interfacing device is provided, which receives at its input an input signal and provides at its output, an output signal to an external load. The output interfacing device invertes the effect of the capacitance of the external load on the slew rate of the output signal.

Abstract: A method for automatic detection of the network data rate and for configuration at the detected data rate by a device connected to the network. This method includes an initialisation phase and an interative processing phase. The initialisation phase includes the following steps: the device is put into listening mode, in which it can receive messages from the network but it cannot send messages on the network; the device is initialised with an initial data rate configuration; a first timeout is started.

Abstract: A microcontroller is provided, which includes a control unit (UC), at least one digital to analog converter (DAC) as a peripheral of the said control unit, and a buffer register located between the said control unit and the said converter, receiving data and a first command to transfer the said data from the said control unit. The microcontroller includes means of synchronisation of the said converter including a register inserted between the said buffer register and the said converter, the said register receiving a second transfer command independent of the said control unit.

Abstract: The disclosure relates to a device for comparing two words, N and P, of n bits each. The device includes at least one comparator block comprising n basic comparator blocks which can each be used to compare bits Ni and Pi of digit place i of words N and P, whereby 0=i=n?1. Moreover, each basic comparator block comprises: a first sub-block which can be used to generate a first signal indicating whether or not bits Ni and Pi are equal, said signal being generated at the output of the sub-block forming a first output (OUT_XORi) of the basic comparator block; a second sub-block which can be used to generate a second signal indicating which enables the second signal to pass to a second output (SOUTi) of the basic comparator block if the first signal indicates that bits Ni and Pi are not equal and which, in the opposite case, enables the second signal to be blocked.

Abstract: A method is provided for managing at least one transition in a three-phase BLDC motor describing a cycle including six successive states, wherein the motor obtains first, second and third synchronisation signals. The synchronisation signals are respectively associated with first, second and third coils of the motor. The method includes the following steps, for each current transition associated with the switching of the motor from a current state to a next state: selecting a current synchronisation signal on which the current transition is to appear; detecting the occurrence of the current transition on the current synchronisation signal; and sending, to the motor, at least one current control signal so as to switch the motor from the current state to the next state.

Abstract: A device is provided for resetting an integrated circuit generating a reset signal after a power supply voltage drop to a very low level has been detected. Such a device includes at least one control means, the state of which (conducting or non-conducting) is controlled by a control voltage equal to the difference between the power supply voltage and a predetermined offset voltage, such that if the control voltage is less than or equal to a threshold, the control means authorizes activation of the means for generating a reset signal.

Abstract: A method for optimising writing by a master block into an interfacing device between the master block and a slave block. The method includes a step for transformation of a code into assembler language, done before the code in machine language is obtained and including the following steps: transformation of all static unit writes comprising more than one word from the assembler language code into one-word static unit writes; search for each set of N successive static one-word unit writes; replace at least one set of N successive static one-word unit writes by one static unit N-word write of, in the assembler language code, where N is an integer greater than or equal to 2.

Abstract: An output buffer is provided, to which first and second input signals are applied and that delivers an output signal. The output buffer includes a second offset switching stage installed in cascade downstream from a first switching stage. The second offset switching stage generates control points shifted in time with respect to memory points.

Abstract: The disclosure relates to a reverse Polish notation processing device making it possible to execute a set of instructions and implementing management of a stack whose size is variable. The device includes a storage device including a random access memory; a device for managing a stack pointer, which is a physical address, in said random access memory, associated with a reference stage of the stack; and a device for managing reference element pointer(s), which is a physical address, in said random access memory, associated with one reference element among elements of a given table contained in the stack. The processing device can execute at least one table-handling instruction with respect to the reference element pointer(s).

Abstract: This disclosure relates to an electronic driver device for an external load to which an input signal is applied at its input and that produces an output signal to the external load from its output. Such an electronic driver device includes elements that reduce dependence of the slew rate of the output signal on the external load capacitance.