Abstract: A semiconductor circuit arrangement providing enhanced security has a first circuitry portion (12) on a semiconductor wafer (10), a second circuitry portion (16) on the wafer separate from the first circuitry portion, the second circuitry portion being coupled (26) to the first circuitry portion and containing access circuitry for allowing access to thereto, and the second circuitry portion being disposed on the wafer such that it can be destructively removed therefrom to leave the first portion of semiconductor circuitry inaccessible through the second portion of semiconductor circuitry. Isolation circuitry (30) is provided for electrically isolating the first circuitry portion following destructive removal of the second circuitry portion.

Abstract: A method of communicating with a plurality of contactless data carriers and a contactless data carrier for use in communicating with a base station. The method of communicating includes the base station transmitting a wake up signal for a plurality of contactless data carriers which are in a wait state. Then, the data carriers exit the wait state and transmit identity information to the base station in a time slot that is randomly self-assigned. The base station registers the identity information by polling the registered data carriers and initiates dialogue with registered data carriers in an order determined by the randomly self-assigned time slots of the registered data carriers. The method of communication helps to avoid the problem of data collision that often occurs when multiple contactless data carriers or smart cards operate in the field of a single base station or card reader.

Abstract: A light detection device has a biasing transistor (1) arranged to provide a bias current and a reverse biased transistor. The reverse biased transistor has a drain terminal (6) coupled via a high impedance resistor (4) to the supply voltage. Incident visible light is detected by a voltage drop at the drain electrode.

Abstract: A co-processor (FIG. 2) for performing modular multiplication comprising: means for receiving B and N binary data streams (bstr, nstr); means for receiving a data value A; adder means (Add1, Add2), subtractor means (Sub1, Sub2, Sub3) and multiplier means (Mul1, Mul2) coupled to sequentially process the B and N binary data streams and the data value A to produce a modulo-reduced multiplication value (A*B) mod N; and further including exponentiation means (FIG. 6) comprising: random access memory (E-RAM) for holding an exponent value; parallel-serial interface means for receiving in parallel from the random access memory the exponent value and for producing therefrom a binary data stream E; control means (CONTROL) for receiving the binary data stream E and for initiating a squaring or a multiply operation in dependence on the value of each bit thereof.