Abstract: A row addressing circuit for DRAM memory is disclosed. Additional address or mode bits are used to dynamically select between long page and short page access modes, and to dynamically select between single cell per bit and dual, or two cell per bit modes in each memory bank within a memory block. In the short page access mode, only one wordline in a memory block is activated. In the long page access mode, two wordlines in the memory block are activated for accessing twice the number of bits as in short page access mode. In the single cell per bit mode, one bit of data is stored in one DRAM cell. In the two cell per bit mode, the row addressing circuit simultaneously activates two wordlines in a bank of the memory block to access one DRAM cell connected to each bitline of a pair of complementary bitlines for writing and reading complementary data. The row addressing circuit can combine the different access modes for system design flexibility.

Abstract: A high-density folded bitline memory array architecture is disclosed. High memory cell packing density is achieved by dividing polysilicon wordlines into short individual segments in the folded bitline scheme. Each wordline segment forms the gate of one or two DRAM memory cell transistors, and each segment is connected to a metal wordline, or conductor having low resistivity. By eliminating spaces between the memory cells due to passing wordlines, a cell arrangement and density similar to open bitline schemes is achieved. Further packing is obtained by arranging two columns of memory cells parallel to each bitline, each column offset with the other by a predetermined pitch. Therefore, by increasing the number of memory cells connected to each complementary bitline pair, each bitline pair can be cut in half and connected to its own bitline sense amplifier to reduce the bitline capacitance.

Abstract: A high-density folded bitline memory array architecture is disclosed. High memory cell packing density is achieved by dividing polysilicon wordlines into short individual segments in the folded bitline scheme. Each wordline segment forms the gate of one or two DRAM memory cell transistors, and each segment is connected to a metal wordline, or conductor having low resistivity. By eliminating spaces between the memory cells due to passing wordlines, a cell arrangement and density similar to open bitline schemes is achieved. Further packing is obtained by arranging two columns of memory cells parallel to each bitline, each column offset with the other by a predetermined pitch. Therefore, by increasing the number of memory cells connected to each complementary bitline pair, each bitline pair can be cut in half and connected to its own bitline sense amplifier to reduce the bitline capacitance.

Abstract: A DRAM having integration capacitors coupled to dummy memory cells of a folded bitline arrangement is disclosed. The dummy memory cells are identical to normal memory cells, and store a midpoint voltage via equalisation between the dummy memory cell having a logic “1” voltage potential and the dummy memory cell having a logic “0” voltage potential. The integration capacitor shares charge with both dummy cell storage capacitors during an equalisation operation to compensate for bitline voltage differences during various access cycle.

Abstract: A high density wordline strapping arrangement is obtained by routing three primary metal-2 wordline straps in the same space as four polysilicon wordline, and routing the fourth wordline strap in a metal-4 layer over the primary metal-2 wordline straps. Stitches in metal-3 connect metal-2 primary wordline straps to metal-4 wordline straps. Therefore, contact spacing and metal pitch limitations are relaxed to allow four metal wordline straps to occupy the same pitch as four polysilicon wordlines. The wordlines are twisted to keep the fully balanced and to minimise coupling between wordline straps and neighbouring power and signal lines. Hence, a smaller memory cell array can be formed according to the wordline packing arrangement of the present invention.

Abstract: A circuit for linearizing the power output of a thyristor uses a threshold switch to pulse the thyristor into the conducting mode. An accumulating capacitor provides a current to operate the threshold switch. The current that charges the accumulating capacitor arises in a DC amplifier and absolute value of sine current source. The accumulating capacitor may discharge either through the threshold switch or through a shunt switch if the threshold has not been attained within a predetermined time period. The timing device for the shunt switch is a sync pulse supply that keys off the absolute value of sine current source.