Abstract: Performing RC analysis in a hierarchical circuit design includes: accessing hierarchical circuit data in the hierarchical circuit design, the hierarchical circuit data comprising top-level data and lower-level block data; obtaining hierarchical RC information; combining RC information on boundary paths between blocks and RC information on boundary paths within blocks to generate boundary RC information; performing RC analysis using the boundary RC information to determine a timing delay; and comparing the timing delay with a desired delay to determine whether an RC timing is closed.

Abstract: Modifying a circuit includes: obtaining timing information of the circuit, wherein the timing information includes timing information pertaining to a critical path of the circuit; determining a scope associated with the critical path, the scope including a subset of the circuit; and performing a fix based at least in part on physical information associated with the circuit to improve timing of the scope.

Abstract: Place-and-route (P&R) includes maintaining a set of local arrival time information and local required time information associated with a circuit layout; determining a candidate fix on a critical path in the circuit layout; statistically determining, using one or more computer processors, a set of one or more adjusted local slacks associated with a region affected by the candidate fix; and in the event that the set of one or more adjusted local slacks indicates that the candidate fix results in a timing improvement, accepting the candidate fix.

Abstract: Modifying a hierarchical circuit design includes accessing hierarchical circuit data in a hierarchical circuit design comprising top level block data and lower level block data; performing timing analysis on a selected portion of the hierarchical circuit data to determine whether timing closure is achieved; and in the event that timing closure is not achieved, determining, within a top level design process, an optimization move on the selected portion of the hierarchical circuit data; wherein the selected portion of the hierarchical circuit data includes a selected portion of the top level block data and a selected portion of the lower level block data.

Abstract: A route technique includes: receiving an input specifying a plurality of semiconductor device components and their logical connections; determining route information pertaining to a plurality of routes that connect in one or more metal layers the semiconductor device components according to their logical connections, the determination being based at least in part on a plurality of predefined tracks associated with a metal layer; and outputting at least a portion of the route information. A first portion of the plurality of predefined tracks corresponds to a first color and a second portion of the plurality of predefined tracks corresponds to a second color.

Abstract: Place-and-route (P&R) includes maintaining a set of local arrival time information and local required time information associated with a circuit layout; determining a candidate fix on a critical path in the circuit layout; statistically determining, using one or more computer processors, a set of one or more adjusted local slacks associated with a region affected by the candidate fix; and in the event that the set of one or more adjusted local slacks indicates that the candidate fix results in a timing improvement, accepting the candidate fix.

Abstract: Modifying a hierarchical circuit design includes: accessing hierarchical circuit data in the hierarchical circuit design; performing timing analysis on a selected portion of the hierarchical circuit data to determine whether inter-block timing closure is achieved; and in the event that inter-block timing closure is not achieved, performing a set of one or more fixes on the selected portion of the hierarchical circuit data to achieve inter-block timing closure. The selected portion of the hierarchical circuit data includes a selected portion of top-level block data and a selected portion of lower-level block data. Accessing hierarchical circuit data, performing timing analysis, and in the event that inter-block timing closure is not achieved, performing the set of one or more fixes are performed within a top-level design process.

Abstract: Modifying a hierarchical circuit design includes accessing hierarchical circuit data in the hierarchical circuit design; performing timing analysis and modifications on a selected portion of the hierarchical circuit data to achieve inter-block timing closure; and performing timing analysis and modifications on the hierarchical circuit data, while accounting for a modification made on the selected portion of the hierarchical circuit data, to achieve intra-block timing closure.